Change in coreboot[master]: mb/google/volteer/var/voema: Enable RTD3 for the NVMe device
David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48848 )
Change subject: mb/google/volteer/var/voema: Enable RTD3 for the NVMe device ......................................................................
mb/google/volteer/var/voema: Enable RTD3 for the NVMe device
Enable Runtime D3 for voema that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168 --- M src/mainboard/google/volteer/variants/voema/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48848/1
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 9efcdb2..8d05c32 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -81,6 +81,14 @@ device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy.
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Tim Wawrzynczak, Paul Fagerburg,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48848
to look at the new patch set (#2).
Change subject: mb/google/volteer/var/voema: Enable RTD3 for the NVMe device ......................................................................
mb/google/volteer/var/voema: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state.
BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168 --- M src/mainboard/google/volteer/variants/voema/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48848/2
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Tim Wawrzynczak, Paul Fagerburg,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48848
to look at the new patch set (#3).
Change subject: mb/google/volteer/var/voema: Enable RTD3 for the NVMe device ......................................................................
mb/google/volteer/var/voema: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state.
BUG=b:169356808 TEST=tested on voema
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168 --- M src/mainboard/google/volteer/variants/voema/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48848/3
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48848 )
Change subject: mb/google/volteer/var/voema: Enable RTD3 for the NVMe device ......................................................................
Patch Set 3: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48848 )
Change subject: mb/google/volteer/var/voema: Enable RTD3 for the NVMe device ......................................................................
Patch Set 3: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48848 )
Change subject: mb/google/volteer/var/voema: Enable RTD3 for the NVMe device ......................................................................
mb/google/volteer/var/voema: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state.
BUG=b:169356808 TEST=tested on voema
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48848 Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/voema/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Paul Fagerburg: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 9efcdb2..8d05c32 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -81,6 +81,14 @@ device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy.
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David Wu (Code Review) -
Hung-Te Lin (Code Review)
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Paul Fagerburg (Code Review)
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Tim Wawrzynczak (Code Review)