hakim giydan (hgiydan@marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15335
-gerrit
commit 07be4d89f5a863b2449cb2a4678bd9a6d1d384b5 Author: Hakim Giydan hgiydan@marvell.com Date: Tue Jul 5 13:33:46 2016 -0700
arch: Add ARMv7-R configuration
This change adds armv7-r configuration for romstage and verstage, and any other files needed to initialize an amrv7-r processor
ARMv7-R is an ARM processor based on the Cortex-R series
Currently, there is already support for the Cortex-M series, so the same files had been renamed and reused for Cortex-R series as well
Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885 Signed-off-by: Hakim Giydan hgiydan@marvell.com --- src/arch/arm/armv7/Kconfig | 8 +++ src/arch/arm/armv7/Makefile.inc | 33 +++++++++-- src/arch/arm/armv7/bootblock_m.S | 50 ---------------- src/arch/arm/armv7/bootblock_m_r.S | 50 ++++++++++++++++ src/arch/arm/armv7/cache_m.c | 79 ------------------------- src/arch/arm/armv7/cache_m_r.c | 79 +++++++++++++++++++++++++ src/arch/arm/armv7/cpu_r.S | 116 +++++++++++++++++++++++++++++++++++++ src/arch/arm/armv7/exception_m.c | 36 ------------ src/arch/arm/armv7/exception_m_r.c | 36 ++++++++++++ util/xcompile/xcompile | 3 +- 10 files changed, 320 insertions(+), 170 deletions(-)
diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig index 0ab3542..4fe3fd7 100644 --- a/src/arch/arm/armv7/Kconfig +++ b/src/arch/arm/armv7/Kconfig @@ -19,3 +19,11 @@ config ARCH_BOOTBLOCK_ARMV7_M config ARCH_VERSTAGE_ARMV7_M def_bool n select ARCH_VERSTAGE_ARM + +config ARCH_VERSTAGE_ARMV7_R + def_bool n + select ARCH_VERSTAGE_ARM + +config ARCH_ROMSTAGE_ARMV7_R + def_bool n + select ARCH_ROMSTAGE_ARM diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 2e9c49c..1b5ce93 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -3,6 +3,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2013 The ChromiumOS Authors +## Copyright (C) 2016 Marvell Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -18,9 +19,10 @@ armv7_flags = -mthumb -I$(src)/arch/arm/include/armv7/ -D__COREBOOT_ARM_ARCH__=7 armv7-a_flags = -march=armv7-a $(armv7_flags) armv7-m_flags = -march=armv7-m $(armv7_flags) +armv7-r_flags = -march=armv7-r $(armv7_flags)
armv7_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated - +armv7-r_asm_flags = $(armv7-r_flags) $(armv7_asm_flags) ############################################################################### # bootblock ############################################################################### @@ -44,10 +46,10 @@ bootblock-generic-ccopts += $(armv7-m_flags) bootblock-S-ccopts += $(armv7_asm_flags)
ifneq ($(CONFIG_BOOTBLOCK_CUSTOM),y) -bootblock-y += bootblock_m.S +bootblock-y += bootblock_m_r.S endif -bootblock-y += exception_m.c -bootblock-y += cache_m.c +bootblock-y += exception_m_r.c +bootblock-y += cache_m_r.c
endif # CONFIG_ARCH_BOOTBLOCK_ARMV7
@@ -73,6 +75,17 @@ libverstage-S-ccopts += $(armv7_asm_flags) verstage-generic-ccopts += $(armv7-m_flags) verstage-S-ccopts += $(armv7_asm_flags)
+else ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7_R),y) +libverstage-generic-ccopts += $(armv7-r_flags) +libverstage-S-ccopts += $(armv7-r_asm_flags) +verstage-generic-ccopts += $(armv7-r_flags) +verstage-S-ccopts += $(armv7-r_asm_flags) + +verstage-y += cache_m_r.c +verstage-y += cpu_r.S +verstage-y += exception_m_r.c +verstage-y += mmu.c + endif # CONFIG_ARCH_VERSTAGE_ARMV7_M
################################################################################ @@ -91,6 +104,18 @@ romstage-S-ccopts += $(armv7_asm_flags) rmodules_arm-generic-ccopts += $(armv7-a_flags) rmodules_arm-S-ccopts += $(armv7_asm_flags)
+else ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7_R),y) +romstage-y += cache_m_r.c +romstage-y += cpu_r.S +romstage-y += exception_m_r.c +romstage-y += mmu.c + +romstage-generic-ccopts += $(armv7-r_flags) +romstage-S-ccopts += $(armv7-r_asm_flags) + +rmodules_arm-generic-ccopts += $(armv7-r_flags) +rmodules_arm-S-ccopts += $(armv7-r_asm_flags) + endif # CONFIG_ARCH_ROMSTAGE_ARMV7
############################################################################### diff --git a/src/arch/arm/armv7/bootblock_m.S b/src/arch/arm/armv7/bootblock_m.S deleted file mode 100644 index 2e46ca0..0000000 --- a/src/arch/arm/armv7/bootblock_m.S +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include <arch/asm.h> - -ENTRY(_start) - /* - * Initialize the stack to a known value. This is used to check for - * stack overflow later in the boot process. - */ - ldr r0, =_stack - ldr r1, =_estack - ldr r2, =0xdeadbeef -init_stack_loop: - str r2, [r0] - add r0, #4 - cmp r0, r1 - bne init_stack_loop - -call_bootblock: - ldr sp, =_estack /* Set up stack pointer */ - bl main -ENDPROC(_start) diff --git a/src/arch/arm/armv7/bootblock_m_r.S b/src/arch/arm/armv7/bootblock_m_r.S new file mode 100644 index 0000000..2e46ca0 --- /dev/null +++ b/src/arch/arm/armv7/bootblock_m_r.S @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include <arch/asm.h> + +ENTRY(_start) + /* + * Initialize the stack to a known value. This is used to check for + * stack overflow later in the boot process. + */ + ldr r0, =_stack + ldr r1, =_estack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + +call_bootblock: + ldr sp, =_estack /* Set up stack pointer */ + bl main +ENDPROC(_start) diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c deleted file mode 100644 index ec8a970..0000000 --- a/src/arch/arm/armv7/cache_m.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * cache.c: Cache maintenance routines for ARMv7-M - */ - -#include <stdint.h> - -#include <arch/cache.h> - -void tlb_invalidate_all(void) -{ -} - -void dcache_clean_all(void) -{ -} - -void dcache_clean_invalidate_all(void) -{ -} - -void dcache_invalidate_all(void) -{ -} - -unsigned int dcache_line_bytes(void) -{ - return 0; -} - -void dcache_clean_by_mva(void const *addr, size_t len) -{ -} - -void dcache_clean_invalidate_by_mva(void const *addr, size_t len) -{ -} - -void dcache_invalidate_by_mva(void const *addr, size_t len) -{ -} - -void dcache_mmu_disable(void) -{ -} - -void dcache_mmu_enable(void) -{ -} - -void cache_sync_instructions(void) -{ -} diff --git a/src/arch/arm/armv7/cache_m_r.c b/src/arch/arm/armv7/cache_m_r.c new file mode 100644 index 0000000..d584465 --- /dev/null +++ b/src/arch/arm/armv7/cache_m_r.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.c: Cache maintenance routines for ARMv7-M & ARMv7-R + */ + +#include <stdint.h> + +#include <arch/cache.h> + +void tlb_invalidate_all(void) +{ +} + +void dcache_clean_all(void) +{ +} + +void dcache_clean_invalidate_all(void) +{ +} + +void dcache_invalidate_all(void) +{ +} + +unsigned int dcache_line_bytes(void) +{ + return 0; +} + +void dcache_clean_by_mva(void const *addr, size_t len) +{ +} + +void dcache_clean_invalidate_by_mva(void const *addr, size_t len) +{ +} + +void dcache_invalidate_by_mva(void const *addr, size_t len) +{ +} + +void dcache_mmu_disable(void) +{ +} + +void dcache_mmu_enable(void) +{ +} + +void cache_sync_instructions(void) +{ +} diff --git a/src/arch/arm/armv7/cpu_r.S b/src/arch/arm/armv7/cpu_r.S new file mode 100644 index 0000000..5c53def --- /dev/null +++ b/src/arch/arm/armv7/cpu_r.S @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/asm.h> + +ENTRY(cpu_disable_dcache) + + /* Read System Control Register configuration dat */ + mrc p15, 0, R0, c1, c0, 0 + + bic R0, R0, #0x1 <<2 + dsb + + /* disable data cache */ + mcr p15, 0, R0, c1, c0, 0 + + bx lr + +ENDPROC(cpu_disable_dcache) + +ENTRY(cpu_enable_dcache) + + /* Read System Control Register configuration data */ + mcr p15, 0, R1, c1, c0, 0 + + orr R1, R1, #0x1 <<2 + mov R0, #0 + dsb + + /* Invalidate entire data cache */ + mcr p15, 0, r0, c15, c5, 0 + + /* enabled data cache */ + mcr p15, 0, R1, c1, c0, 0 + + bx lr + +ENDPROC(cpu_enable_dcache) + +ENTRY(cpu_disable_icache) + + /* Read System Control Register configuration data */ + mcr p15, 0, R0, c1, c0, 0 + + /* enable instruction cache */ + bic R0, R0, #0x1 <<12 + + /* disable instruction cache */ + mcr p15, 0, R0, c1, c0, 0 + + isb + + bx lr + +ENDPROC(cpu_disable_icache) + +ENTRY(cpu_enable_icache) + + /* Read System Control Register configuration data */ + mrc p15, 0, R1, c1, c0, 0 + + /* enable instruction cache */ + orr R1, R1, #0x1 <<12 + + mov R0, #0 + + /* Invalidate entire instruction cache */ + mcr p15, 0, r0, c7, c5, 0 + + /* enable instruction cache */ + mcr p15, 0, R1, c1, c0, 0 + + isb + + bx lr + +ENDPROC(cpu_enable_icache) + +ENTRY(cpu_init) + + mrc p15,0,r0,c9,c14,0 + mov r0, $1 + mcr p15,0,r0,c9,c14,0 + + /* read performance monitor control register into R0 */ + mrc p15, 0, r0, c9, c12, 0 + + /* set the enable-bit for the performance counters and cycle counter */ + orr r0, r0, #1 + + /* write the perfomance monitor control register back */ + mcr p15, 0, r0, c9, c12, 0 + + /* load the bit-mask into r0 */ + mov r0, #0x80000000 + + /* write the bit-mask to the enable set register + * and enable cycle counter bit + */ + mcr p15, 0, r0, c9, c12, 1 + + bx lr + +ENDPROC(cpu_init) diff --git a/src/arch/arm/armv7/exception_m.c b/src/arch/arm/armv7/exception_m.c deleted file mode 100644 index d76cc6a..0000000 --- a/src/arch/arm/armv7/exception_m.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <arch/exception.h> -#include <console/console.h> - -void exception_init(void) -{ - printk(BIOS_DEBUG, "Exception handlers not installed.\n"); -} diff --git a/src/arch/arm/armv7/exception_m_r.c b/src/arch/arm/armv7/exception_m_r.c new file mode 100644 index 0000000..d76cc6a --- /dev/null +++ b/src/arch/arm/armv7/exception_m_r.c @@ -0,0 +1,36 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/exception.h> +#include <console/console.h> + +void exception_init(void) +{ + printk(BIOS_DEBUG, "Exception handlers not installed.\n"); +} diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 13a0e8f..c030545 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -5,6 +5,7 @@ # Copyright (C) 2007-2010 coresystems GmbH # Copyright (C) 2012 Google Inc # Copyright (C) 2016 Raptor Engineering, LLC +# Copyright (C) 2016 Marvell Inc # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -316,7 +317,7 @@ arch_config_arm() { TBFDARCHS="littlearm" TCLIST="armv7-a armv7a arm" TWIDTH="32" - TSUPP="arm armv4 armv7 armv7_m" + TSUPP="arm armv4 armv7 armv7_m armv7_r" TABI="eabi" }
-
hakim giydan