[M] Change in coreboot[master]: arch/x86/postcar_loader: Don't add postcar to stage cache

[Reka Norman (Code Review)]

Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68641 )

Change subject: arch/x86/postcar_loader: Don't add postcar to stage cache
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Patch Set 3:

(1 comment)

Patchset:

PS2:
> I got confused myself. Using stage cache is indeed a performance optimisation, but in order for that to be secure it has to reside in TSEG. So not using stage cache has no security implications.

Oh ok, in that case what do you think about this change?
> Also whether reading from cached SPI flash (with prefetch enabled) is faster than reading uncached DRAM is probably platform dependent.

I understand, and platforms can enable the config if it benefits them. But I still think disabling it is a better default. If SPI if faster than uncached memory on some platforms and slower on others, then let's say on average across platforms they're the same speed (is that reasonable?).

If we add postcar to stage cache we do 2 operations on boot (read from SPI, write to memory) and 1 operation on resume (read from memory).

If we don't add postcar, we only do 1 operation on boot, and 1 on resume.

So on average we'd save some boot time while not affecting resume time.
> I think it's not a bad idea to attempt skipping it as indeed FSP puts things in memory and not coreboot.

Ok, makes sense. We should do that if/when we decide to enable caching in romstage then. But for nissa at least, the total boot time will still be better if we don't add postcar to stage cache at all (either via this CL or selecting NO_STAGE_CACHE).