Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39445 )
Change subject: soc/intel/tigerlake: fix PCI interrupts for D31 ......................................................................
soc/intel/tigerlake: fix PCI interrupts for D31
Fix interrupt for eSPI, P2SB, PMC and HDA
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Id37c88c1ed9436626651ebd22156403dd94978b7 --- M src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl M src/soc/intel/tigerlake/include/soc/irq_tgl.h 2 files changed, 8 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39445/1
diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl index 8aadf8d..6440127 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl @@ -17,10 +17,11 @@ #include <soc/irq.h>
Name (PICP, Package () { - /* D31:HSA, SMBUS, TraceHUB */ + /* D31: eSPI, P2SB, PMC, HDA */ + Package(){0x001FFFFF, 0, 0, eSPI_IRQ }, + Package(){0x001FFFFF, 1, 0, P2SB_IRQ }, + Package(){0x001FFFFF, 2, 0, PMC_IRQ }, Package(){0x001FFFFF, 3, 0, HDA_IRQ }, - Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, - Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, /* D30: UART0, UART1, SPI0, SPI1 */ Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, diff --git a/src/soc/intel/tigerlake/include/soc/irq_tgl.h b/src/soc/intel/tigerlake/include/soc/irq_tgl.h index 0ea6053..7d0bd95 100644 --- a/src/soc/intel/tigerlake/include/soc/irq_tgl.h +++ b/src/soc/intel/tigerlake/include/soc/irq_tgl.h @@ -36,9 +36,10 @@ #define LPSS_UART1_IRQ 35 #define LPSS_UART2_IRQ 33
-#define HDA_IRQ 16 -#define SMBUS_IRQ 16 -#define TRACEHUB_IRQ 16 +#define eSPI_IRQ 16 +#define P2SB_IRQ 17 +#define PMC_IRQ 18 +#define HDA_IRQ 19
#define PCIE_1_IRQ 16 #define PCIE_2_IRQ 17
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39445
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Fix PCI interrupts for D31 ......................................................................
soc/intel/tigerlake: Fix PCI interrupts for D31
Fix interrupt for eSPI, P2SB, PMC and HDA
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Id37c88c1ed9436626651ebd22156403dd94978b7 --- M src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl M src/soc/intel/tigerlake/include/soc/irq_tgl.h 2 files changed, 8 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39445/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39445 )
Change subject: soc/intel/tigerlake: Fix PCI interrupts for D31 ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl:
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/acp... PS2, Line 22: Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, : Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, Why were these removed?
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/acp... PS2, Line 21: Package(){0x001FFFFF, 0, 0, eSPI_IRQ }, : Package(){0x001FFFFF, 1, 0, P2SB_IRQ }, : Package(){0x001FFFFF, 2, 0, PMC_IRQ }, As per https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon..., it looks like eSPI, P2SB and PMC don't use interrupts.
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/irq_tgl.h:
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/inc... PS2, Line 42: #define HDA_IRQ 19 Did you verify interrupts work correctly for HDA? It looks like this is different than what is seen in FSP: https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon...
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39445 )
Change subject: soc/intel/tigerlake: Fix PCI interrupts for D31 ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl:
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/acp... PS2, Line 22: Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, : Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
Why were these removed?
We're referring with BIOS asl file and i has this setting which is same as exiting code base. And we're verifying audio for checking HDA irq. It looks interrupt setting in https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon... is wrong.
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/acp... PS2, Line 21: Package(){0x001FFFFF, 0, 0, eSPI_IRQ }, : Package(){0x001FFFFF, 1, 0, P2SB_IRQ }, : Package(){0x001FFFFF, 2, 0, PMC_IRQ },
As per https://github. […]
We're referring with BIOS asl file and i has this setting which is same as exiting code base. And we're verifying audio for checking HDA irq. It looks interrupt setting in https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon... is wrong.
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/irq_tgl.h:
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/inc... PS2, Line 42: #define HDA_IRQ 19
Did you verify interrupts work correctly for HDA? It looks like this is different than what is seen […]
We're referring with BIOS asl file and i has this setting which is same as exiting code base. And we're verifying audio for checking HDA irq. It looks interrupt setting in https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon... is wrong.
Usually IRQ is assigned 16,17,18,19 for func 0,1,2,3 and HDA audio 19 is working in internal baseline. We'll verify audio with interrupt value 19.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39445 )
Change subject: soc/intel/tigerlake: Fix PCI interrupts for D31 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl:
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/acp... PS2, Line 21: Package(){0x001FFFFF, 0, 0, eSPI_IRQ }, : Package(){0x001FFFFF, 1, 0, P2SB_IRQ }, : Package(){0x001FFFFF, 2, 0, PMC_IRQ },
We're referring with BIOS asl file and i has this setting which is same as exiting code base. […]
So, which setting is taking effect? Can you please point me to the right code?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39445 )
Change subject: soc/intel/tigerlake: Fix PCI interrupts for D31 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl:
https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/acp... PS2, Line 21: Package(){0x001FFFFF, 0, 0, eSPI_IRQ }, : Package(){0x001FFFFF, 1, 0, P2SB_IRQ }, : Package(){0x001FFFFF, 2, 0, PMC_IRQ },
So, which setting is taking effect? Can you please point me to the right code?
It's not part of FSP code but FSP wrapper code. I'll create partner bug to share part of code.
Wonkyu Kim has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39445 )
Change subject: soc/intel/tigerlake: Fix PCI interrupts for D31 ......................................................................
Abandoned
-
Furquan Shaikh (Code Review) -
Wonkyu Kim (Code Review)