Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45696 )
Change subject: mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params ......................................................................
mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params
Some Librem Minis exhibit issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this, so limiting SATA speeds to 3Gbps is no longer needed.
Test: build/boot Librem Mini with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7
Change-Id: I8b3cbcff7f181bcab35d71e859033578c822bb20 Signed-off-by: Matt DeVillier matt.devillier@puri.sm --- M src/mainboard/purism/librem_whl/ramstage.c M src/mainboard/purism/librem_whl/romstage.c 2 files changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45696/1
diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_whl/ramstage.c index 07ede66..56ed1b7 100644 --- a/src/mainboard/purism/librem_whl/ramstage.c +++ b/src/mainboard/purism/librem_whl/ramstage.c @@ -10,7 +10,4 @@ size_t num_gpios; const struct pad_config *gpio_table = variant_gpio_table(&num_gpios); cnl_configure_pads(gpio_table, num_gpios); - - /* Limit SATA speed to 3Gbps until correct HSIO PHY settings determined */ - params->SataSpeedLimit = 2; } diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_whl/romstage.c index 9f8d600..c45f138 100644 --- a/src/mainboard/purism/librem_whl/romstage.c +++ b/src/mainboard/purism/librem_whl/romstage.c @@ -48,5 +48,12 @@
void mainboard_memory_init_params(FSPM_UPD *memupd) { - cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + cannonlake_memcfg_init(mem_cfg, &memcfg); + + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; }
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45696 )
Change subject: mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45696/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_whl/romstage.c:
https://review.coreboot.org/c/coreboot/+/45696/1/src/mainboard/purism/librem... PS1, Line 58: mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; IIRC one of these two ports is on a cable. As per guidelines, I think it should be 2 or 3 instead. The M.2 port should be fine with 1, though.
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45696
to look at the new patch set (#2).
Change subject: mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params ......................................................................
mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params
Some Librem Minis exhibit issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this, so limiting SATA speeds to 3Gbps is no longer needed.
Test: build/boot Librem Mini with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7
Change-Id: I8b3cbcff7f181bcab35d71e859033578c822bb20 Signed-off-by: Matt DeVillier matt.devillier@puri.sm --- M src/mainboard/purism/librem_whl/ramstage.c M src/mainboard/purism/librem_whl/romstage.c 2 files changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45696/2
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45696 )
Change subject: mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45696/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_whl/romstage.c:
https://review.coreboot.org/c/coreboot/+/45696/1/src/mainboard/purism/librem... PS1, Line 58: mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1;
IIRC one of these two ports is on a cable. As per guidelines, I think it should be 2 or 3 instead. […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45696 )
Change subject: mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45696 )
Change subject: mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params ......................................................................
mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params
Some Librem Minis exhibit issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this, so limiting SATA speeds to 3Gbps is no longer needed.
Test: build/boot Librem Mini with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7
Change-Id: I8b3cbcff7f181bcab35d71e859033578c822bb20 Signed-off-by: Matt DeVillier matt.devillier@puri.sm Reviewed-on: https://review.coreboot.org/c/coreboot/+/45696 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/purism/librem_whl/ramstage.c M src/mainboard/purism/librem_whl/romstage.c 2 files changed, 8 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_whl/ramstage.c index 07ede66..56ed1b7 100644 --- a/src/mainboard/purism/librem_whl/ramstage.c +++ b/src/mainboard/purism/librem_whl/ramstage.c @@ -10,7 +10,4 @@ size_t num_gpios; const struct pad_config *gpio_table = variant_gpio_table(&num_gpios); cnl_configure_pads(gpio_table, num_gpios); - - /* Limit SATA speed to 3Gbps until correct HSIO PHY settings determined */ - params->SataSpeedLimit = 2; } diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_whl/romstage.c index 9f8d600..3a3ca6b 100644 --- a/src/mainboard/purism/librem_whl/romstage.c +++ b/src/mainboard/purism/librem_whl/romstage.c @@ -48,5 +48,12 @@
void mainboard_memory_init_params(FSPM_UPD *memupd) { - cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + cannonlake_memcfg_init(mem_cfg, &memcfg); + + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 2; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; }