Change in coreboot[master]: soc/intel/common: Add Elkhartlake Device IDs

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37652 )

Change subject: soc/intel/common: Add Elkhartlake Device IDs
......................................................................

soc/intel/common: Add Elkhartlake Device IDs

Add Elkhartlake CPU, SA and PCH IDs

Signed-off-by: Lean Sheng Tan 
Change-Id: I66f6ff8c85612076fbfebff4ab00842783201710
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
22 files changed, 120 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/37652/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 43752f8..9270689 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2811,6 +2811,14 @@
 #define PCI_DEVICE_ID_INTEL_TGP_ESPI_26	0xA09F
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1	0x3887
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2	0x4d80
+#define PCI_DEVICE_ID_INTEL_MCC_ESPI_0			0x4b00
+#define PCI_DEVICE_ID_INTEL_MCC_ESPI_1			0x4b04
+#define PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI		0x4b03
+#define PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI	0x4b02
+#define PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI		0x4b01
+#define PCI_DEVICE_ID_INTEL_MCC_ESPI_2			0x4b05
+#define PCI_DEVICE_ID_INTEL_MCC_ESPI_3			0x4b06
+#define PCI_DEVICE_ID_INTEL_MCC_ESPI_4			0x4b07

/* Intel PCIE device ids  */
 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1		0x9d10
@@ -3015,6 +3023,14 @@
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7		0x38be
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8		0x38bf

+#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1		0x4b38
+#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2		0x4b39
+#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP3		0x4b3a
+#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP4		0x4b3b
+#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP5		0x4b3c
+#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6		0x4b3d
+#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7		0x4b3e
+
 /* Intel SATA device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_U_SATA		0x9d03
 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA		0x9d07
@@ -3047,6 +3063,7 @@
 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA	0xa0d7
 #define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA	0x282a
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA		0x38d3
+#define PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA	0x4b60

/* Intel PMC device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC		0x9d21
@@ -3062,6 +3079,7 @@
 #define PCI_DEVICE_ID_INTEL_CMP_PMC		0x02a1
 #define PCI_DEVICE_ID_INTEL_TGP_PMC		0xa0a1
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC		0x38a1
+#define PCI_DEVICE_ID_INTEL_MCC_PMC		0x4b21

/* Intel I2C device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_I2C0		0x9d60
@@ -3120,7 +3138,14 @@
 #define PCI_DEVICE_ID_INTEL_TGP_I2C5		0xa0c6
 #define PCI_DEVICE_ID_INTEL_TGP_I2C6		0xa0d8
 #define PCI_DEVICE_ID_INTEL_TGP_I2C7		0xa0d9
-
+#define PCI_DEVICE_ID_INTEL_MCC_I2C0		0x4b78
+#define PCI_DEVICE_ID_INTEL_MCC_I2C1		0x4b79
+#define PCI_DEVICE_ID_INTEL_MCC_I2C2		0x4b7a
+#define PCI_DEVICE_ID_INTEL_MCC_I2C3		0x4b7b
+#define PCI_DEVICE_ID_INTEL_MCC_I2C4		0x4b4b
+#define PCI_DEVICE_ID_INTEL_MCC_I2C5		0x4b4c
+#define PCI_DEVICE_ID_INTEL_MCC_I2C6		0x4b44
+#define PCI_DEVICE_ID_INTEL_MCC_I2C7		0x4b45
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0		0x38e8
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1		0x38e9
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2		0x38ea
@@ -3161,7 +3186,9 @@
 #define PCI_DEVICE_ID_INTEL_TGP_UART0		0xa0a8
 #define PCI_DEVICE_ID_INTEL_TGP_UART1		0xa0a9
 #define PCI_DEVICE_ID_INTEL_TGP_UART2		0xa0c7
-
+#define PCI_DEVICE_ID_INTEL_MCC_UART0		0x4b28
+#define PCI_DEVICE_ID_INTEL_MCC_UART1		0x4b29
+#define PCI_DEVICE_ID_INTEL_MCC_UART2		0x4b4d
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0		0x38a8
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1		0x38a9
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2		0x38c7
@@ -3203,7 +3230,10 @@
 #define PCI_DEVICE_ID_INTEL_TGP_GSPI4		0xa0fe
 #define PCI_DEVICE_ID_INTEL_TGP_GSPI5		0xa0de
 #define PCI_DEVICE_ID_INTEL_TGP_GSPI6		0xa0df
-
+#define PCI_DEVICE_ID_INTEL_MCC_SPI0		0x4b24
+#define PCI_DEVICE_ID_INTEL_MCC_GSPI0		0x4b2a
+#define PCI_DEVICE_ID_INTEL_MCC_GSPI1		0x4b2b
+#define PCI_DEVICE_ID_INTEL_MCC_GSPI2		0x4b37
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0		0x38aa
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1		0x38ab
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2		0x38fb
@@ -3313,6 +3343,12 @@
 #define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT			0x9A52
 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULX			0x9A40
 #define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0		0x4569
+#define PCI_DEVICE_ID_INTEL_EHL_GT1_1			0x4541
+#define PCI_DEVICE_ID_INTEL_EHL_GT2_1			0x4540
+#define PCI_DEVICE_ID_INTEL_EHL_GT1_2			0x4551
+#define PCI_DEVICE_ID_INTEL_EHL_GT2_2			0x4550
+#define PCI_DEVICE_ID_INTEL_EHL_GT1_3			0x4571
+#define PCI_DEVICE_ID_INTEL_EHL_GT2_3			0x4570

/* Intel Northbridge Ids */
 #define PCI_DEVICE_ID_INTEL_APL_NB		0x5af0
@@ -3368,6 +3404,8 @@
 #define PCI_DEVICE_ID_INTEL_TGL_ID_U		0x9A14
 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1		0x9A12
 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y		0x9A10
+#define PCI_DEVICE_ID_INTEL_JSL_EHL			0x4532
+#define PCI_DEVICE_ID_INTEL_EHL_ID_1		0x4510
 #define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD	0x4e2a

/* Intel SMBUS device Ids */
@@ -3380,6 +3418,7 @@
 #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS		0x34a3
 #define PCI_DEVICE_ID_INTEL_CMP_SMBUS			0x02a3
 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS		0xa0a3
+#define PCI_DEVICE_ID_INTEL_MCC_SMBUS			0x4b23
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS		0x38a3

/* Intel XHCI device Ids */
@@ -3395,6 +3434,7 @@
 #define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI		0x34ed
 #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI		0x02ed
 #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI		0xa0ed
+#define PCI_DEVICE_ID_INTEL_MCC_XHCI		0x4b7d
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI	0x38ed

/* Intel P2SB device Ids */
@@ -3410,6 +3450,7 @@
 #define PCI_DEVICE_ID_INTEL_ICL_P2SB		0x34a0
 #define PCI_DEVICE_ID_INTEL_CMP_P2SB		0x02a0
 #define PCI_DEVICE_ID_INTEL_TGL_P2SB		0xa0a0
+#define PCI_DEVICE_ID_INTEL_EHL_P2SB		0x4b20
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB	0x38a0

/* Intel SRAM device Ids */
@@ -3420,6 +3461,7 @@
 #define PCI_DEVICE_ID_INTEL_ICL_SRAM		0x34ef
 #define PCI_DEVICE_ID_INTEL_CMP_SRAM		0x02ef
 #define PCI_DEVICE_ID_INTEL_TGL_SRAM		0xa0ef
+#define PCI_DEVICE_ID_INTEL_MCC_SRAM		0x4b7f
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM	0x38ef

/* Intel AUDIO device Ids */
@@ -3436,6 +3478,7 @@
 #define PCI_DEVICE_ID_INTEL_CMP_AUDIO		0x02c8
 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO		0x2284
 #define PCI_DEVICE_ID_INTEL_TGL_AUDIO		0xa0c8
+#define PCI_DEVICE_ID_INTEL_MCC_AUDIO		0x4b55
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO	0x38c8

/* Intel HECI/ME device Ids */
@@ -3453,6 +3496,10 @@
 #define PCI_DEVICE_ID_INTEL_ICL_CSE0		0x34e0
 #define PCI_DEVICE_ID_INTEL_CMP_CSE0		0x02e0
 #define PCI_DEVICE_ID_INTEL_TGL_CSE0		0xa0e0
+#define PCI_DEVICE_ID_INTEL_MCC_CSE0		0x4b70
+#define PCI_DEVICE_ID_INTEL_MCC_CSE1		0x4b71
+#define PCI_DEVICE_ID_INTEL_MCC_CSE2		0x4b74
+#define PCI_DEVICE_ID_INTEL_MCC_CSE3		0x4b75
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0	0x38e0

/* Intel XDCI device Ids */
@@ -3464,6 +3511,7 @@
 #define PCI_DEVICE_ID_INTEL_ICP_LP_XDCI		0x34ee
 #define PCI_DEVICE_ID_INTEL_CMP_LP_XDCI		0x02ee
 #define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI		0xa0ee
+#define PCI_DEVICE_ID_INTEL_MCC_XDCI		0x4b7e

/* Intel SD device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_SD		0x5aca
@@ -3473,6 +3521,7 @@
 #define PCI_DEVICE_ID_INTEL_CNP_H_SD		0xa375
 #define PCI_DEVICE_ID_INTEL_ICL_SD		0x34f8
 #define PCI_DEVICE_ID_INTEL_CMP_SD		0x02f5
+#define PCI_DEVICE_ID_INTEL_MCC_SD		0x4b48
 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD	0x38f8

/* Intel EMMC device Ids */
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 721e42c..f3c6c7d 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -87,6 +87,7 @@
    { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 },
    { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 },
    { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 },
+	{ X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 },
    { 0, 0 },
 };

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 6aaba40..ecc2e38 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -756,6 +756,10 @@
    PCI_DEVICE_ID_INTEL_CMP_CSE0,
    PCI_DEVICE_ID_INTEL_TGL_CSE0,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0,
+	PCI_DEVICE_ID_INTEL_MCC_CSE0,
+	PCI_DEVICE_ID_INTEL_MCC_CSE1,
+	PCI_DEVICE_ID_INTEL_MCC_CSE2,
+	PCI_DEVICE_ID_INTEL_MCC_CSE3,
    0,
 };

diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c
index 6c00ed1..6240129 100644
--- a/src/soc/intel/common/block/dsp/dsp.c
+++ b/src/soc/intel/common/block/dsp/dsp.c
@@ -36,6 +36,7 @@
    PCI_DEVICE_ID_INTEL_ICL_AUDIO,
    PCI_DEVICE_ID_INTEL_TGL_AUDIO,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO,
+	PCI_DEVICE_ID_INTEL_MCC_AUDIO,
    0,
 };

diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index cbe189c..3a117a0 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -214,6 +214,12 @@
    PCI_DEVICE_ID_INTEL_TGL_GT2_ULX,
    PCI_DEVICE_ID_INTEL_TGL_GT3_ULT,
    PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0,
+	PCI_DEVICE_ID_INTEL_EHL_GT1_1,
+	PCI_DEVICE_ID_INTEL_EHL_GT2_1,
+	PCI_DEVICE_ID_INTEL_EHL_GT1_2,
+	PCI_DEVICE_ID_INTEL_EHL_GT2_2,
+	PCI_DEVICE_ID_INTEL_EHL_GT1_3,
+	PCI_DEVICE_ID_INTEL_EHL_GT2_3,
    0,
 };

diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c
index 4a87e1a..20a06dd 100644
--- a/src/soc/intel/common/block/hda/hda.c
+++ b/src/soc/intel/common/block/hda/hda.c
@@ -83,6 +83,7 @@
    PCI_DEVICE_ID_INTEL_CMP_AUDIO,
    PCI_DEVICE_ID_INTEL_BSW_AUDIO,
    PCI_DEVICE_ID_INTEL_TGL_AUDIO,
+	PCI_DEVICE_ID_INTEL_MCC_AUDIO,
    0
 };

diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index bc692d3..3ff1ac3 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -249,6 +249,14 @@
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5,
+	PCI_DEVICE_ID_INTEL_MCC_I2C0,
+	PCI_DEVICE_ID_INTEL_MCC_I2C1,
+	PCI_DEVICE_ID_INTEL_MCC_I2C2,
+	PCI_DEVICE_ID_INTEL_MCC_I2C3,
+	PCI_DEVICE_ID_INTEL_MCC_I2C4,
+	PCI_DEVICE_ID_INTEL_MCC_I2C5,
+	PCI_DEVICE_ID_INTEL_MCC_I2C6,
+	PCI_DEVICE_ID_INTEL_MCC_I2C7,
    0,
 };

diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
index aaf1793..e0b0d8c 100644
--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -54,6 +54,7 @@
 #define CPUID_COMETLAKE_H_S_10_2_P0	0xa0651
 #define CPUID_COMETLAKE_H_S_10_2_Q0_P1	0xa0654
 #define CPUID_TIGERLAKE_A0	0x806c0
+#define CPUID_ELKHARTLAKE_A0	0x90660

/*
  * MP Init callback function to Find CPU Topology. This function is common
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index 258975c..40192fd 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -224,6 +224,14 @@
    PCI_DEVICE_ID_INTEL_TGP_ESPI_26,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2,
+	PCI_DEVICE_ID_INTEL_MCC_ESPI_0,
+	PCI_DEVICE_ID_INTEL_MCC_ESPI_1,
+	PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI,
+	PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI,
+	PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI,
+	PCI_DEVICE_ID_INTEL_MCC_ESPI_2,
+	PCI_DEVICE_ID_INTEL_MCC_ESPI_3,
+	PCI_DEVICE_ID_INTEL_MCC_ESPI_4,
    0
 };

diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index 75c74f2..032ed7d 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -181,6 +181,7 @@
    PCI_DEVICE_ID_INTEL_CMP_P2SB,
    PCI_DEVICE_ID_INTEL_TGL_P2SB,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB,
+	PCI_DEVICE_ID_INTEL_EHL_P2SB,
    0,
 };

diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index ecc1fcb..37ebeda 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -274,6 +274,13 @@
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8,
+	PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1,
+	PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2,
+	PCI_DEVICE_ID_INTEL_MCC_PCIE_RP3,
+	PCI_DEVICE_ID_INTEL_MCC_PCIE_RP4,
+	PCI_DEVICE_ID_INTEL_MCC_PCIE_RP5,
+	PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6,
+	PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7,
    0
 };

diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index 1645070..9ea66f3 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -135,6 +135,7 @@
    PCI_DEVICE_ID_INTEL_CMP_PMC,
    PCI_DEVICE_ID_INTEL_TGP_PMC,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC,
+	PCI_DEVICE_ID_INTEL_MCC_PMC,
    0
 };

diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c
index 0f26262..814c040 100644
--- a/src/soc/intel/common/block/sata/sata.c
+++ b/src/soc/intel/common/block/sata/sata.c
@@ -101,6 +101,7 @@
    PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA,
    PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA,
+	PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA,
    0
 };

diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c
index e94e4e9..c73d6e1 100644
--- a/src/soc/intel/common/block/scs/sd.c
+++ b/src/soc/intel/common/block/scs/sd.c
@@ -74,6 +74,7 @@
    PCI_DEVICE_ID_INTEL_ICL_SD,
    PCI_DEVICE_ID_INTEL_CMP_SD,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD,
+	PCI_DEVICE_ID_INTEL_MCC_SD,
    0
 };

diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index c9a6b17..88aafc4 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -97,6 +97,7 @@
    PCI_DEVICE_ID_INTEL_CMP_SMBUS,
    PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS,
+	PCI_DEVICE_ID_INTEL_MCC_SMBUS,
    0
 };

diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c
index eedde75..a953b66 100644
--- a/src/soc/intel/common/block/spi/spi.c
+++ b/src/soc/intel/common/block/spi/spi.c
@@ -93,6 +93,10 @@
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI,
+	PCI_DEVICE_ID_INTEL_MCC_SPI0,
+	PCI_DEVICE_ID_INTEL_MCC_GSPI0,
+	PCI_DEVICE_ID_INTEL_MCC_GSPI1,
+	PCI_DEVICE_ID_INTEL_MCC_GSPI2,
    0
 };

diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c
index 9e44fa3..e59391e 100644
--- a/src/soc/intel/common/block/sram/sram.c
+++ b/src/soc/intel/common/block/sram/sram.c
@@ -53,6 +53,7 @@
    PCI_DEVICE_ID_INTEL_CMP_SRAM,
    PCI_DEVICE_ID_INTEL_TGL_SRAM,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM,
+	PCI_DEVICE_ID_INTEL_MCC_SRAM,
    0,
 };

diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 2019ef6..323c271 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -368,6 +368,8 @@
    PCI_DEVICE_ID_INTEL_TGL_ID_U_1,
    PCI_DEVICE_ID_INTEL_TGL_ID_Y,
    PCI_DEVICE_ID_INTEL_JSL_PRE_PROD,
+	PCI_DEVICE_ID_INTEL_JSL_EHL,
+	PCI_DEVICE_ID_INTEL_EHL_ID_1,
    0
 };

diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 4053516..b62adb4 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -281,6 +281,9 @@
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2,
+	PCI_DEVICE_ID_INTEL_MCC_UART0,
+	PCI_DEVICE_ID_INTEL_MCC_UART1,
+	PCI_DEVICE_ID_INTEL_MCC_UART2,
    0,
 };

diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c
index 92f3b15..2496081 100644
--- a/src/soc/intel/common/block/xdci/xdci.c
+++ b/src/soc/intel/common/block/xdci/xdci.c
@@ -44,6 +44,7 @@
    PCI_DEVICE_ID_INTEL_ICP_LP_XDCI,
    PCI_DEVICE_ID_INTEL_CMP_LP_XDCI,
    PCI_DEVICE_ID_INTEL_TGP_LP_XDCI,
+	PCI_DEVICE_ID_INTEL_MCC_XDCI,
    0
 };

diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index af4d132..0ad1ead 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -133,6 +133,7 @@
    PCI_DEVICE_ID_INTEL_CMP_LP_XHCI,
    PCI_DEVICE_ID_INTEL_TGP_LP_XHCI,
    PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI,
+	PCI_DEVICE_ID_INTEL_MCC_XHCI,
    0
 };

diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c
index 3d856a5..bf425c7 100644
--- a/src/soc/intel/tigerlake/bootblock/report_platform.c
+++ b/src/soc/intel/tigerlake/bootblock/report_platform.c
@@ -38,6 +38,7 @@
    const char *name;
 } cpu_table[] = {
    { CPUID_TIGERLAKE_A0, "Tigerlake A0" },
+	{ CPUID_ELKHARTLAKE_A0, "Elkhartlake A0" },
 };

static struct {
@@ -48,6 +49,8 @@
    { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" },
    { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" },
    { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, "Jasperlake Pre Prod" },
+	{ PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" },
+	{ PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" },
 };

static struct {
@@ -88,6 +91,11 @@
    { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" },
    { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, "Jasperlake Pre Prod" },
    { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, "Jasperlake Pre Prod" },
+	{ PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" },
+	{ PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" },
+	{ PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" },
+	{ PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI, "Elkhartlake Premium" },
+	{ PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI, "Elkhartlake Super" },
 };

static struct {
@@ -99,6 +107,12 @@
    { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" },
    { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" },
    { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, "Jasperlake Pre Prod GT0" },
+	{ PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" },
+	{ PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" },
+	{ PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" },
+	{ PCI_DEVICE_ID_INTEL_EHL_GT2_2, "Elkhartlake GT2 2" },
+	{ PCI_DEVICE_ID_INTEL_EHL_GT1_3, "Elkhartlake GT1 3" },
+	{ PCI_DEVICE_ID_INTEL_EHL_GT2_3, "Elkhartlake GT2 3" },
 };

static inline uint8_t get_dev_revision(pci_devfn_t dev)

[Werner Zeh (Code Review)]

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37652 )

Change subject: soc/intel/common: Add Elkhartlake Device IDs
......................................................................

Patch Set 1: Code-Review+1

What does MCC stand for? Why do you not use EHL instead?

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37652 )

Change subject: soc/intel/common: Add Elkhartlake Device IDs
......................................................................

Patch Set 1:

(3 comments)

Please mention in the commit message what MCC stands for.

https://review.coreboot.org/c/coreboot/+/37652/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37652/1//COMMIT_MSG@7 
PS1, Line 7: Elkhartlake
Elkhart Lake?

https://review.coreboot.org/c/coreboot/+/37652/1/src/soc/intel/common/block/... 
File src/soc/intel/common/block/systemagent/systemagent.c:

https://review.coreboot.org/c/coreboot/+/37652/1/src/soc/intel/common/block/... 
PS1, Line 371: 	PCI_DEVICE_ID_INTEL_JSL_EHL,
Unrelated?

https://review.coreboot.org/c/coreboot/+/37652/1/src/soc/intel/tigerlake/boo... 
File src/soc/intel/tigerlake/bootblock/report_platform.c:

https://review.coreboot.org/c/coreboot/+/37652/1/src/soc/intel/tigerlake/boo... 
PS1, Line 52: 	{ PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" },
Please elaborate in the commit message.

[Lean Sheng Tan (Code Review)]

Hello Werner Zeh, Patrick Rudolph, Subrata Banik, Ronak Kanabar, Aamir Bohra, Maulik V Vaghela, V Sowmya, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37652

to look at the new patch set (#2).

Change subject: soc/intel/common: Add Elkhartlake Device IDs
......................................................................

soc/intel/common: Add Elkhartlake Device IDs

Add Elkhartlake CPU, SA and PCH IDs.
EHL PCH is code named as MCC.
Also added a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs.

Signed-off-by: Lean Sheng Tan 
Change-Id: I66f6ff8c85612076fbfebff4ab00842783201710
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
22 files changed, 120 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/37652/2

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37652 )

Change subject: soc/intel/common: Add Elkhartlake Device IDs
......................................................................

Patch Set 2:
> Patch Set 1: Code-Review+1
>
> What does MCC stand for? Why do you not use EHL instead?

MCC is the PCH name. updated in the commit message.

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37652 )

Change subject: soc/intel/common: Add Elkhartlake Device IDs
......................................................................

Patch Set 2:

(3 comments)

https://review.coreboot.org/c/coreboot/+/37652/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37652/1//COMMIT_MSG@7 
PS1, Line 7: Elkhartlake
> Elkhart Lake?

Using the same format as previous intel patches, jasperlake, tigerlake, cannonlake etc.

https://review.coreboot.org/c/coreboot/+/37652/1/src/soc/intel/common/block/... 
File src/soc/intel/common/block/systemagent/systemagent.c:

https://review.coreboot.org/c/coreboot/+/37652/1/src/soc/intel/common/block/... 
PS1, Line 371: 	PCI_DEVICE_ID_INTEL_JSL_EHL,
> Unrelated?

updated in commit message, this MCH id is shared between JSL and EHL SKUs.

https://review.coreboot.org/c/coreboot/+/37652/1/src/soc/intel/tigerlake/boo... 
File src/soc/intel/tigerlake/bootblock/report_platform.c:

https://review.coreboot.org/c/coreboot/+/37652/1/src/soc/intel/tigerlake/boo... 
PS1, Line 52: 	{ PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" },
> Please elaborate in the commit message.

Done

[Werner Zeh (Code Review)]

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37652 )

Change subject: soc/intel/common: Add Elkhartlake Device IDs
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37652/1/src/include/device/pci_ids.... 
File src/include/device/pci_ids.h:

https://review.coreboot.org/c/coreboot/+/37652/1/src/include/device/pci_ids.... 
PS1, Line 2817: #define PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI	0x4b02
Adjust the number of tabs here?

https://review.coreboot.org/c/coreboot/+/37652/1/src/include/device/pci_ids.... 
PS1, Line 3407: 	
Adjust the tabs here

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37652 )

Change subject: soc/intel/common: Add Elkhartlake Device IDs
......................................................................

Abandoned