Change in coreboot[master]: arm64: Align cache maintenance code with libpayload and ARM32

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19785 )

Change subject: arm64: Align cache maintenance code with libpayload and ARM32
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/19785/1/src/arch/arm64/armv8/cache.c
File src/arch/arm64/armv8/cache.c:

Line 126: 	else if (sctlr & SCTLR_I)
> But isn't that happening with clean_invalidate_all() as well with the scena
> Or did you mean that since there are lines fetched from the instruction fetch sitting in l2 the caches need to be invalided to pick up the new instructions sitting in ram at the same address?

Yes, the invalidate is the important part so that instruction fetches see the new code that's only in RAM. Honestly, I'm not sure why this is clean_invalidate instead of just invalidate... it probably doesn't make a difference because without data caching the cache lines couldn't become dirty anyways, so the clean might be a no-op. This is just what the Qualcomm guy uploaded back then and said fixes the issue on his board that I don't have, so I'd rather unify the implementations on that now and it can still be revisited if we find issues with it in the future.