New patch to review for coreboot: 01bf702 Intel Sandy Bridge: udelay.c: Change comparison from <= to <

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3259

-gerrit

commit 01bf702129e14941f6fc8692c6110a7bf5a56f1f
Author: Paul Menzel 
Date:   Fri May 17 17:25:25 2013 +0200

Intel Sandy Bridge: udelay.c: Change comparison from <= to <

Currently code in `udelay.c` differs between the Intel northbridges
    GM45, 945 on the one hand and Sandy Bridge on the other hand.

The reason for this is that a wrong comparison > was used.

The following commit

commit 784ffb3db694dd2c964d9a4e1c6657a835b2d141
        Author: Sven Schnelle 
        Date:   Tue Jan 10 12:16:38 2012 +0100

i945: fix tsc udelay()

Reviewed-on: http://review.coreboot.org/530

fixed the sign from > to <, whereas Stefan Reinauer changed it from
    > to <= before adding the Sandy Bridge port in the following commit.

commit 00636b0daefc3c499990744226a0e1a316d71731
        Author: Stefan Reinauer 
        Date:   Wed Apr 4 00:08:51 2012 +0200

Add support for Intel Sandybridge CPU (northbridge part)

Reviewed-on: http://review.coreboot.org/854

As there are no technical reasons for this difference, unify this
    between the chipsets. See the discussion of the other patch set in
    Gerrit [1].

[1] http://review.coreboot.org/#/c/3220/1/src/northbridge/intel/i5000/udelay.c

Change-Id: I64f2aa1db114ad2e9f34181c5f3034f6a8414a11
    Signed-off-by: Paul Menzel 
---
 src/northbridge/intel/sandybridge/udelay.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
index 670898a..608726c 100644
--- a/src/northbridge/intel/sandybridge/udelay.c
+++ b/src/northbridge/intel/sandybridge/udelay.c
@@ -51,5 +51,5 @@ void udelay(u32 us)
    do {
    	tsc = rdtsc();
    } while ((tsc.hi < tsc1.hi)
-		 || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo)));
+		 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
 }