Change in coreboot[master]: mb/google/brya/var/brask: Set PL and PsysPL

[Alan Huang (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Alan Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59576 )

Change subject: mb/google/brya/var/brask: Set PL and PsysPL
......................................................................

mb/google/brya/var/brask: Set PL and PsysPL

Set the defalut PL1, PL2 and PL4 according to Intel's spec.
Set PsysPL2 and PsysPmax according to Brask's spec.

BUG=b:193864533
BRANCH=none
TEST=Compare the measured power from adapter with the value of 'psys'
     from the command 'dump_intel_rapl_consumption'.

Signed-off-by: Alan Huang 
Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56
---
M src/mainboard/google/brya/variants/brask/Makefile.inc
A src/mainboard/google/brya/variants/brask/ramstage.c
2 files changed, 57 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59576/1

diff --git a/src/mainboard/google/brya/variants/brask/Makefile.inc b/src/mainboard/google/brya/variants/brask/Makefile.inc
index d38141c..bc39984 100644
--- a/src/mainboard/google/brya/variants/brask/Makefile.inc
+++ b/src/mainboard/google/brya/variants/brask/Makefile.inc
@@ -4,3 +4,4 @@
 romstage-y += gpio.c

ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/brask/ramstage.c b/src/mainboard/google/brya/variants/brask/ramstage.c
new file mode 100644
index 0000000..73b1d7b
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brask/ramstage.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 5000, 45000, 80000, 80000, 159000 },
+};
+
+const struct system_power_limits sys_limits[] = {
+	/* SKU_ID, TDP (Watts), psys_pl2 (Watts), psys_pmax (Watts) */
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135, 257 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135, 257 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 230, 257 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 230, 257 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 230, 257 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 230, 257 },
+};
+
+/*
+ * Psys_pmax considerations.
+ *
+ * Given the hardware design in brask, the serial shunt resistor is 0.005ohm.
+ * The full scale of hardware PSYS signal 1.6v maps to system current 13.52A
+ * instead of real system power. The equation is shown below:
+ * PSYS = 1.6v = (0.005ohm x 13.52A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510)
+ * R501/(R501 + R510) = 0.47 = 15K / (15K + 16.9K)
+ * Since there is no voltage information from PSYS, different voltage input
+ * would map to different Psys_pmax settings:
+ * For Type-C 15V, the Psys_pmax sholud be 15v x 13.52A = 202.8W
+ * For Type-C 20V, the Psys_pmax should be 20v x 13.52A = 270.4W
+ * For a barrel jack, the Psys_pmax should be 19.5v x 13.52A = 263.6W
+ */
+const struct psys_config psys_config = {
+	.efficiency = 97,
+	.psys_imax_ma = 13520,
+	.bj_volts_mv = 19500
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
+	variant_update_power_limits(limits, total_entries);
+}