Change in coreboot[master]: src/soc/intel/tigerlake: Add ACPI LPIT table

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: src/soc/intel/tigerlake: Add ACPI LPIT table
......................................................................

src/soc/intel/tigerlake: Add ACPI LPIT table

This patch adds support for Low Power S0 idle Device Specific Method
in LPIT table. This provides OSPM with s0ix entry and exit
hooks. These LPIT S0ix entry and exit hooks call platform specific
methods (MS0X) for s0ix entry and exit, when they exist

BUG=b:148892882
BRANCH=none
TEST="BUILD to check if is successful"

Signed-off-by: Venkata Krishna Nimmagadda 
Change-Id: Ib58f2e33a33bac9cc5f6aca28e85a8066413a5cf
---
A src/soc/intel/tigerlake/acpi/lpit.asl
1 file changed, 73 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/40259/1

diff --git a/src/soc/intel/tigerlake/acpi/lpit.asl b/src/soc/intel/tigerlake/acpi/lpit.asl
new file mode 100644
index 0000000..78a728c
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/lpit.asl
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+External(_SB.MS0X, MethodObj)
+
+scope(_SB)
+{
+	Device(LPID) {
+	Name(_ADR, 0x00000000)
+	Name(_CID, EISAID("PNP0D80"))
+	Name(UUID,
+		ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))
+		Method(_DSM, 4) {
+			If(Arg0 == ^UUID) {
+			/*
+			 * Enum functions
+			 */
+			If(Arg2 == Zero) {
+				Return(Buffer(One) {
+				       0x60}
+				)
+			}
+			/*
+			 * Function 1 - Get Device Constraints
+			 */
+			If(Arg2 == 1) {
+				Return(Package(5) {
+				       0, Ones, Ones, Ones, Ones}
+				)
+			}
+			/*
+			 * Function 2 - Get Crash Dump Device
+			 */
+			If(Arg2 == 2) {
+				Return(Buffer(One) {
+				       0x0}
+				)
+			}
+			/*
+			 * Function 3 - Display Off Notification
+			 */
+			If(Arg2 == 3) {
+			}
+			/*
+			 * Function 4 - Display On Notification
+			 */
+			If(Arg2 == 4) {
+			}
+			/*
+			 * Function 5 - Low Power S0 Entry Notification
+			 */
+			If(Arg2 == 5) {
+
+				/* provide board level s0ix hook */
+				If (CondRefOf (_SB.MS0X)) {
+					_SB.MS0X(1)
+				}
+			}
+			/*
+			 * Function 6 - Low Power S0 Exit Notification
+			 */
+			If(Arg2 == 6) {
+
+				/* provide board level s0ix hook */
+				If (CondRefOf (_SB.MS0X)) {
+					_SB.MS0X(0)
+				}
+			}
+		}
+		Return(Buffer(One) {0x00})
+		}		// Method(_DSM)
+	}			// device (LPID)
+}				// End Scope(_SB)

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: src/soc/intel/tigerlake: Add ACPI LPIT table
......................................................................

Patch Set 1: Code-Review+1

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: src/soc/intel/tigerlake: Add ACPI LPIT table
......................................................................

Patch Set 1:

(9 comments)

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@7 
PS1, Line 7: src/
Remove.

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@10 
PS1, Line 10: in LPIT table. This provides OSPM with s0ix entry and exit
Is that defined in the ACPI spec? Why is it not done in the operating system?

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@12 
PS1, Line 12: s0ix
S0ix

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@12 
PS1, Line 12: methods (MS0X) for s0ix entry and exit, when they exist
Please add a dot/period at the end of sentences.

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@9 
PS1, Line 9: This patch adds support for Low Power S0 idle Device Specific Method
           : in LPIT table. This provides OSPM with s0ix entry and exit
           : hooks. These LPIT S0ix entry and exit hooks call platform specific
           : methods (MS0X) for s0ix entry and exit, when they exist
Please re-flow for 72/75 charcaters per line.

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@13 
PS1, Line 13: 
Is this just boiler plate or is it actually doing something. Shouldn’t an ACPI generator be implemented, once such methods should be created?

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@16 
PS1, Line 16: BUILD to check if is successful
build is enough.

https://review.coreboot.org/c/coreboot/+/40259/1/src/soc/intel/tigerlake/acp... 
File src/soc/intel/tigerlake/acpi/lpit.asl:

https://review.coreboot.org/c/coreboot/+/40259/1/src/soc/intel/tigerlake/acp... 
PS1, Line 54: s0ix
S0ix

https://review.coreboot.org/c/coreboot/+/40259/1/src/soc/intel/tigerlake/acp... 
PS1, Line 64: s0ix
S0ix

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: src/soc/intel/tigerlake: Add ACPI LPIT table
......................................................................

Patch Set 1:

Could we add this to soc/intel/common ? It looks identical (minus the call to _SB.PCI0.LPCB.EC0.S0IX) to cannonlake.

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Venkata Krishna Nimmagadda (Code Review)]

Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40259

to look at the new patch set (#2).

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

soc/intel/common: Add _DSM methods for LPIT table

This patch adds _DSM Method in LPIT table for entering and exiting
S0ix. This method get injected into DSDT table and called from kernel.

LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.

Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.

BUG=b:148892882
BRANCH=none
TEST="BUILD"

Signed-off-by: Venkata Krishna Nimmagadda 
Change-Id: Ib58f2e33a33bac9cc5f6aca28e85a8066413a5cf
---
A src/soc/intel/common/acpi/lpit.asl
1 file changed, 111 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/40259/2

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

Patch Set 2: Code-Review+1

(7 comments)

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@7 
PS1, Line 7: src/
> Remove.

Done

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@10 
PS1, Line 10: in LPIT table. This provides OSPM with s0ix entry and exit
> Is that defined in the ACPI spec? Why is it not done in the operating system?

I have realized that my description was not accurate. I corrected it now.

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@12 
PS1, Line 12: s0ix
> S0ix

Done

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@9 
PS1, Line 9: This patch adds support for Low Power S0 idle Device Specific Method
           : in LPIT table. This provides OSPM with s0ix entry and exit
           : hooks. These LPIT S0ix entry and exit hooks call platform specific
           : methods (MS0X) for s0ix entry and exit, when they exist
> Please re-flow for 72/75 charcaters per line.

Done

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@12 
PS1, Line 12: methods (MS0X) for s0ix entry and exit, when they exist
> Please add a dot/period at the end of sentences.

Done

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@13 
PS1, Line 13:
> Is this just boiler plate or is it actually doing something. […]

This is needed for a short term workaround. This will be included into dsdt.

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@16 
PS1, Line 16: BUILD to check if is successful
> build is enough.

Done

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

Patch Set 2:

(10 comments)

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
File src/soc/intel/common/acpi/lpit.asl:

PS2: 
I realize you're just copying this to common/, but the cleanups I've suggested below would be appreciated!

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 21: scope
Scope

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 23: 	Device(LPID) {
Please put the brace on the next line, and begin indenting there. All three Names below should line up with the Method(_DSM, 4) line.

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 28: 		Method(_DSM, 4) {
Same thing here, brace on the next line please.

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 33: Zero
Maybe some #defines for the enumerated values that are valid for Arg2 would be nice.

#define LPID_DSM_ARG2_ENUM_FUNCTIONS 0
#define LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS 1
... etc.

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 35: 				       0x60}
This can go on the previous line.

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 43: 				       0, Ones, Ones, Ones, Ones}
This can go on the previous line.

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 51: 				       0x0}
This can go on the previous line.

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 108: 		Return(Buffer(One) {0x00})
Blank line before Return.

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 110: device
Device

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Venkata Krishna Nimmagadda (Code Review)]

Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40259

to look at the new patch set (#3).

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

soc/intel/common: Add _DSM methods for LPIT table

This patch adds _DSM Method in LPIT table for entering and exiting
S0ix. This method get injected into DSDT table and called from kernel.

LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.

Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.

BUG=b:148892882
BRANCH=none
TEST="BUILD"

Signed-off-by: Venkata Krishna Nimmagadda 
Change-Id: Ib58f2e33a33bac9cc5f6aca28e85a8066413a5cf
---
A src/soc/intel/common/acpi/lpit.asl
1 file changed, 98 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/40259/3

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

Patch Set 3: Code-Review+1

(11 comments)

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
File src/soc/intel/common/acpi/lpit.asl:

PS2:
> I realize you're just copying this to common/, but the cleanups I've suggested below would be apprec […]

Done

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 21: scope
> Scope

Done

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 28: 		Method(_DSM, 4) {
> Same thing here, brace on the next line please.

Done

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 33: Zero
> Maybe some #defines for the enumerated values that are valid for Arg2 would be nice. […]

Done

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 35: 				       0x60}
> This can go on the previous line.

Done

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 43: 				       0, Ones, Ones, Ones, Ones}
> This can go on the previous line.

Done

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 51: 				       0x0}
> This can go on the previous line.

Done

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 108: 		Return(Buffer(One) {0x00})
> Blank line before Return.

Done

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 110: device
> Device

Done

https://review.coreboot.org/c/coreboot/+/40259/1/src/soc/intel/tigerlake/acp... 
File src/soc/intel/tigerlake/acpi/lpit.asl:

https://review.coreboot.org/c/coreboot/+/40259/1/src/soc/intel/tigerlake/acp... 
PS1, Line 54: s0ix
> S0ix

Done

https://review.coreboot.org/c/coreboot/+/40259/1/src/soc/intel/tigerlake/acp... 
PS1, Line 64: s0ix
> S0ix

Done

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
File src/soc/intel/common/acpi/lpit.asl:

https://review.coreboot.org/c/coreboot/+/40259/2/src/soc/intel/common/acpi/l... 
PS2, Line 23: 	Device(LPID) {
> Please put the brace on the next line, and begin indenting there. […]

Done

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

Patch Set 3:

(5 comments)

Thank you for helping with cleaning this up!

https://review.coreboot.org/c/coreboot/+/40259/3/src/soc/intel/common/acpi/l... 
File src/soc/intel/common/acpi/lpit.asl:

https://review.coreboot.org/c/coreboot/+/40259/3/src/soc/intel/common/acpi/l... 
PS3, Line 37: 2
Can we make a #define for this too?
LPID_DSM_ARG2_GET_CRASH_DUMP_DEV?

https://review.coreboot.org/c/coreboot/+/40259/3/src/soc/intel/common/acpi/l... 
PS3, Line 43: 3
Can we make a #define for this too?
LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY

https://review.coreboot.org/c/coreboot/+/40259/3/src/soc/intel/common/acpi/l... 
PS3, Line 48: 4
Can we make a #define for this too?
LPID_DSM_ARG2_DISPLAY_ON_NOTIFY

https://review.coreboot.org/c/coreboot/+/40259/3/src/soc/intel/common/acpi/l... 
PS3, Line 53: 5
Can we make a #define for this too?
LPID_DSM_ARG2_S0IX_ENTRY

https://review.coreboot.org/c/coreboot/+/40259/3/src/soc/intel/common/acpi/l... 
PS3, Line 76: 6
Can we make a #define for this too?
LPID_DSM_ARG2_S0IX_EXIT

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Venkata Krishna Nimmagadda (Code Review)]

Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40259

to look at the new patch set (#4).

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

soc/intel/common: Add _DSM methods for LPIT table

This patch adds _DSM Method in LPIT table for entering and exiting
S0ix. This method get injected into DSDT table and called from kernel.

LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.

Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.

BUG=b:148892882
BRANCH=none
TEST="BUILD"

Signed-off-by: Venkata Krishna Nimmagadda 
Change-Id: Ib58f2e33a33bac9cc5f6aca28e85a8066413a5cf
---
A src/soc/intel/common/acpi/lpit.asl
1 file changed, 104 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/40259/4

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

Patch Set 4: Code-Review+2

(1 comment)

Thank you!

https://review.coreboot.org/c/coreboot/+/40259/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40259/4//COMMIT_MSG@11 
PS4, Line 11: 
            : LPIT table is hardcoded in this patch but the proper way to implement
            : is to use inject_dsdt to make the _DSM methods available for soc's to
            : implement.
Do you have plans for a follow-up to address this too?

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

Patch Set 4:

(6 comments)

https://review.coreboot.org/c/coreboot/+/40259/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40259/4//COMMIT_MSG@11 
PS4, Line 11: 
            : LPIT table is hardcoded in this patch but the proper way to implement
            : is to use inject_dsdt to make the _DSM methods available for soc's to
            : implement.
> Do you have plans for a follow-up to address this too?

Right, let me try to address it. We can't dodge this forever.But should it be done in this patch itself?

https://review.coreboot.org/c/coreboot/+/40259/3/src/soc/intel/common/acpi/l... 
File src/soc/intel/common/acpi/lpit.asl:

https://review.coreboot.org/c/coreboot/+/40259/3/src/soc/intel/common/acpi/l... 
PS3, Line 37: 2
> Can we make a #define for this too? […]

sorry didn't catch it myself. Done now

https://review.coreboot.org/c/coreboot/+/40259/3/src/soc/intel/common/acpi/l... 
PS3, Line 43: 3
> Can we make a #define for this too? […]

Done

https://review.coreboot.org/c/coreboot/+/40259/3/src/soc/intel/common/acpi/l... 
PS3, Line 48: 4
> Can we make a #define for this too? […]

Done

https://review.coreboot.org/c/coreboot/+/40259/3/src/soc/intel/common/acpi/l... 
PS3, Line 53: 5
> Can we make a #define for this too? […]

Done

https://review.coreboot.org/c/coreboot/+/40259/3/src/soc/intel/common/acpi/l... 
PS3, Line 76: 6
> Can we make a #define for this too? […]

Done

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40259/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40259/4//COMMIT_MSG@11 
PS4, Line 11: 
            : LPIT table is hardcoded in this patch but the proper way to implement
            : is to use inject_dsdt to make the _DSM methods available for soc's to
            : implement.
> Right, let me try to address it. We can't dodge this forever. […]

I think it's fine to address it in another CL.

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

Patch Set 4: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@13 
PS1, Line 13:
> This is needed for a short term workaround. This will be included into dsdt.

I will do a follow-up patch to do this, the right way, using generator.

Change in coreboot[master]: soc/intel/common: Add _DSM methods for LPIT table

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40259 )

Change subject: soc/intel/common: Add _DSM methods for LPIT table
......................................................................

soc/intel/common: Add _DSM methods for LPIT table

This patch adds _DSM Method in LPIT table for entering and exiting
S0ix. This method get injected into DSDT table and called from kernel.

LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.

Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.

BUG=b:148892882
BRANCH=none
TEST="BUILD"

Signed-off-by: Venkata Krishna Nimmagadda 
Change-Id: Ib58f2e33a33bac9cc5f6aca28e85a8066413a5cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40259
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Venkata Krishna Nimmagadda 
---
A src/soc/intel/common/acpi/lpit.asl
1 file changed, 104 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved
  Venkata Krishna Nimmagadda: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/common/acpi/lpit.asl b/src/soc/intel/common/acpi/lpit.asl
new file mode 100644
index 0000000..4f8bd5e
--- /dev/null
+++ b/src/soc/intel/common/acpi/lpit.asl
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#define LPID_DSM_ARG2_ENUM_FUNCTIONS 0
+#define LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS 1
+
+#define LPID_DSM_ARG2_GET_CRASH_DUMP_DEV 2
+#define LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY 3
+#define LPID_DSM_ARG2_DISPLAY_ON_NOTIFY 4
+#define LPID_DSM_ARG2_S0IX_ENTRY 5
+#define LPID_DSM_ARG2_S0IX_EXIT 6
+
+External(_SB.MS0X, MethodObj)
+External(_SB.PCI0.LPCB.EC0.S0IX, MethodObj)
+External(_SB.PCI0.EGPM, MethodObj)
+External(_SB.PCI0.RGPM, MethodObj)
+
+Scope(_SB)
+{
+	Device(LPID)
+	{
+		Name(_ADR, 0x00000000)
+		Name(_CID, EISAID("PNP0D80"))
+		Name(UUID, ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))
+		Method(_DSM, 4)
+		{
+			If(Arg0 == ^UUID) {
+			/*
+			 * Enum functions
+			 */
+			If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) {
+				Return(Buffer(One) {0x60})
+			}
+			/*
+			 * Function 1 - Get Device Constraints
+			 */
+			If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) {
+				Return(Package(5) {0, Ones, Ones, Ones, Ones})
+			}
+			/*
+			 * Function 2 - Get Crash Dump Device
+			 */
+			If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) {
+				Return(Buffer(One) {0x0})
+			}
+			/*
+			 * Function 3 - Display Off Notification
+			 */
+			If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) {
+			}
+			/*
+			 * Function 4 - Display On Notification
+			 */
+			If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) {
+			}
+			/*
+			 * Function 5 - Low Power S0 Entry Notification
+			 */
+			If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) {
+				/* Inform the EC */
+				If (CondRefOf (_SB.PCI0.LPCB.EC0.S0IX)) {
+					_SB.PCI0.LPCB.EC0.S0IX(1)
+				}
+
+				/* provide board level S0ix hook */
+				If (CondRefOf (_SB.MS0X)) {
+					_SB.MS0X(1)
+				}
+
+				/*
+				 * Save the current PM bits then
+				 * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
+ 				 */
+				If (CondRefOf (_SB.PCI0.EGPM))
+				{
+					_SB.PCI0.EGPM ()
+				}
+			}
+			/*
+			 * Function 6 - Low Power S0 Exit Notification
+			 */
+			If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) {
+				/* Inform the EC */
+				If (CondRefOf (_SB.PCI0.LPCB.EC0.S0IX)) {
+					_SB.PCI0.LPCB.EC0.S0IX(0)
+				}
+
+				/* provide board level S0ix hook */
+				If (CondRefOf (_SB.MS0X)) {
+					_SB.MS0X(0)
+				}
+
+				/* Restore GPIO all Community PM */
+				If (CondRefOf (_SB.PCI0.RGPM))
+				{
+					_SB.PCI0.RGPM ()
+				}
+			}
+		}
+
+		Return(Buffer(One) {0x00})
+		}		// Method(_DSM)
+	}			// Device (LPID)
+}				// End Scope(_SB)