Jagadish Krishnamoorthy (jagadish.krishnamoorthy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15871
-gerrit
commit 685ab906bf074486001b32d4aaebbc76c5ac534d Author: Jagadish Krishnamoorthy jagadish.krishnamoorthy@intel.com Date: Mon Jul 25 13:59:44 2016 -0700
soc/intel/apollolake: Configure gpio ownership
For the gpio based irq to work, the ownership of the pad should be changed to GPIO_DRIVER. Provide an option in the gpio defs to configure the PAD onwership.
BUG=chrome-os-partner:54371 TEST=none
Change-Id: I26d242d25d2034049340adf526045308fcdebbc0 Signed-off-by: Jagadish Krishnamoorthy jagadish.krishnamoorthy@intel.com --- src/soc/intel/apollolake/gpio.c | 22 ++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/gpio.h | 8 ++++++++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 9 +++++++++ 3 files changed, 39 insertions(+)
diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index a3ffb3d..14531d7 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -54,6 +54,25 @@ static const struct pad_community *gpio_get_community(uint16_t pad) return map; }
+static void gpio_configure_owner(const struct pad_config *cfg, uint16_t port) +{ + uint16_t pin = gpio_acpi_pin(cfg->pad); + uint16_t reg; + + /* Based on the gpio pin number configure the + * corresponding bit in HostSW_OWN register. + * Value of 0x1 indicates Gpio Driver onwership. + */ + if (pin < 32) + reg = HOSTSW_OWN_0; + else if (pin >= 32 && pin < 64) + reg = HOSTSW_OWN_1; + else if (pin >= 64 && pin < 96) + reg = HOSTSW_OWN_2; + + iosf_write(port, reg, iosf_read(port, reg) | 1 << (pin % 32)); +} + static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, uint16_t pad_cfg_offset) { @@ -91,6 +110,9 @@ void gpio_configure_pad(const struct pad_config *cfg) iosf_write(comm->port, config_offset + sizeof(uint32_t), cfg->config1);
gpio_configure_itss(cfg, comm->port, config_offset); + /* Use the RO bit in pad_config 1 register to indicate the ownership */ + if(cfg->config1 & PAD_CFG1_GPIO_DRIVER) + gpio_configure_owner(cfg, comm->port); }
void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 1ebac2d..3e377c7 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -56,6 +56,14 @@ typedef uint32_t gpio_t; PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull))
+/* General purpose input, Set Host Software Pad Owner to Gpio Driver mode. + * GPIO input event updates are routed to gpio driver. + * Default ownership is Acpi mode. + */ +#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER) /* No Connect configuration for unused pad. * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term */ diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 48e08e7..90ed515 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -45,6 +45,10 @@ #define MISCCFG_GPE0_DW2_SHIFT 16 #define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
+#define HOSTSW_OWN_0 0x80 /*Host Software Pad Ownership for GPIO 0 ~ 31 */ +#define HOSTSW_OWN_1 0x84 /*Host Software Pad Ownership for GPIO 32 ~ 63 */ +#define HOSTSW_OWN_2 0x88 /*Host Software Pad Ownership for GPIO 64 ~ 95 */ + #define PAD_CFG0_TX_STATE (1 << 0) #define PAD_CFG0_RX_STATE (1 << 1) #define PAD_CFG0_TX_DISABLE (1 << 8) @@ -75,6 +79,11 @@ #define PAD_CFG0_RESET_PLTRST (2 << 30) #define PAD_CFG0_RESET_RSMRST (3 << 30)
+/* Use the first bit in IntSel field to indicate gpio + * ownership. This field is RO and hence not used during + gpio configuration. + */ +#define PAD_CFG1_GPIO_DRIVER (0x1 << 0) #define PAD_CFG1_IRQ_MASK (0xff << 0) #define PAD_CFG1_PULL_MASK (0xf << 10) #define PAD_CFG1_PULL_NONE (0x0 << 10)
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Jagadish Krishnamoorthy