Change in coreboot[master]: nb/intel/gm45: Don't use PCI operations on the pci_domain device

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27242

Change subject: nb/intel/gm45: Don't use PCI operations on the pci_domain device
......................................................................

nb/intel/gm45: Don't use PCI operations on the pci_domain device

The pci_domain just happens to have bus, device and function set to 0,
which is why to code works.

This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.

Change-Id: I598b056d5fb1ce23b390b2f0ab4e9fb242d3685a
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/gm45/northbridge.c
1 file changed, 11 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27242/1

diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 4c42513..a3f517b 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -95,16 +95,18 @@

pci_domain_read_resources(dev);

+	struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
+
    /* Top of Upper Usable DRAM, including remap */
-	touud = pci_read_config16(dev, D0F0_TOUUD);
+	touud = pci_read_config16(mch, D0F0_TOUUD);
    touud <<= 20;

/* Top of Lower Usable DRAM */
-	tolud = pci_read_config16(dev, D0F0_TOLUD) & 0xfff0;
+	tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0;
    tolud <<= 16;

/* Top of Memory - does not account for any UMA */
-	tom = pci_read_config16(dev, D0F0_TOM) & 0x1ff;
+	tom = pci_read_config16(mch, D0F0_TOM) & 0x1ff;
    tom <<= 27;

printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
@@ -113,7 +115,7 @@
    tomk = tolud >> 10;

/* Graphics memory comes next */
-	const u16 ggc = pci_read_config16(dev, D0F0_GGC);
+	const u16 ggc = pci_read_config16(mch, D0F0_GGC);
    if (!(ggc & 2)) {
    	printk(BIOS_DEBUG, "IGD decoded, subtracting ");

@@ -129,7 +131,7 @@

uma_sizek = gms_sizek + gsm_sizek;
    }
-	const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);
+	const u8 esmramc = pci_read_config8(mch, D0F0_ESMRAMC);
    const u32 tseg_sizek = decode_tseg_size(esmramc);
    printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10);
    tomk -= tseg_sizek;
@@ -185,10 +187,12 @@
 {
    u32 reg32;

+	struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
+
    /* Enable SERR */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 = pci_read_config32(mch, PCI_COMMAND);
    reg32 |= PCI_COMMAND_SERR;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	pci_write_config32(mch, PCI_COMMAND, reg32);
 }

static struct device_operations pci_domain_ops = {