Change in coreboot[master]: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Subrata Banik, Paul Menzel, Angel Pons, Nick Vaccaro, Eric Lai.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62837 )

Change subject: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
......................................................................

Patch Set 3: Code-Review+2

(1 comment)

File src/soc/intel/common/block/fast_spi/fast_spi.c:

https://review.coreboot.org/c/coreboot/+/62837/comment/7b423a65_52f56d68 
PS3, Line 248: 	if (ENV_PAYLOAD_LOADER) {
             : 		mtrr_use_temp_range(ext_bios_base, ext_bios_size, type);
             : 	} else {
potential optimization for the future: if the extended BIOS window is added into the list of memranges below before the MTRR calls in fast_spi_cache_bios_region(), then the MTRR solution only needs to be calculated one time instead of two.