Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36375 )
Change subject: mb/asrock/h110m: fix gpe0_dw0 option in device tree ......................................................................
mb/asrock/h110m: fix gpe0_dw0 option in device tree
Sets the same value as the vendor’s firmware.
Change-Id: Idd80f6df081d79a158dd56e7e699572554a4ee5e Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/36375/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index acb2a9e..9898d01 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -29,7 +29,7 @@ # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" + register "gpe0_dw0" = "GPP_C" register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E"
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36375 )
Change subject: mb/asrock/h110m: fix gpe0_dw0 option in device tree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36375/2/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/36375/2/src/mainboard/asrock/h110m/... PS2, Line 30: . If this route changes then the affected GPE : # offset bits also need to be changed. anything to do about this?
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Maxim Polyakov (Code Review) -
Patrick Georgi (Code Review)