Patch set updated for coreboot: c86e729 southbridge/amd/pi: Combine and expand the IRQ text strings

[Dave Frodin]

Dave Frodin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8374

-gerrit

commit c86e729824d50b612747c6db19f8ae0a84b256cf
Author: Dave Frodin 
Date:   Fri Feb 6 07:25:11 2015 -0700

southbridge/amd/pi: Combine and expand the IRQ text strings

This expands the table of text descriptions of the
    IRQ assignments. It also combines the strings that are common
    to Avalon and Bolton. The range of values used by Bolton is
    also increased to 128 locations.

Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7
    Signed-off-by: Dave Frodin 
---
 src/southbridge/amd/pi/hudson/amd_pci_int_defs.h  |  2 +-
 src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 24 +++++++++--------------
 2 files changed, 10 insertions(+), 16 deletions(-)

diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
index 78a40f0..ae3c88d 100644
--- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
@@ -73,7 +73,7 @@
 #endif

#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
-#define FCH_INT_TABLE_SIZE 0x54
+#define FCH_INT_TABLE_SIZE 128
 #define PIRQ_GPP0	0x50	/* GPP INT 0 */
 #define PIRQ_GPP1	0x51	/* GPP INT 1 */
 #define PIRQ_GPP2	0x52	/* GPP INT 2 */
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
index 517c892..20e5faf 100644
--- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
@@ -20,26 +20,20 @@
 #ifndef AMD_PCI_INT_TYPES_H
 #define AMD_PCI_INT_TYPES_H

-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
 const char * intr_types[] = {
    [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
    [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
-	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t",
+	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t\t",
    [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
-	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
+	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB","Dev20.5 INTC",
+	[0x7F] = "RSVD\t",
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON)
+	[0x40] = "RSVD\t","SATA\t",
+	[0x62] = "GPIO\t",
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
    [0x40] = "IDE\t", "SATA\t",
-	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t"
-};
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON)
-const char * intr_types[] = {
-	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
-	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
-	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t",
-	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
-	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB",
-	[0x40] = "RSVD\t", "SATA\t",
-	[0x60] = "RSVD\t", "RSVD\t", "GPIO\t",
-};
+	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
 #endif
+};

#endif /* AMD_PCI_INT_TYPES_H */