Change in coreboot[master]: soc/intel/alderlake: Add ADLP 4+4+2 power configurations - coreboot-gerrit

24 Nov 2021


      Attention is currently required from: Paul Menzel, Curtis Chen, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59483 )
Change subject: soc/intel/alderlake: Add ADLP 4+4+2 power configurations
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Patch Set 5: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59483/comment/0ff6b3a2_03c5d8db 
PS3, Line 9: Map exist PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 442
           : sku power related settings.
...
commit msgs are 72 characters wide please
Done
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731
Gerrit-Change-Number: 59483
Gerrit-PatchSet: 5
Gerrit-Owner: Curtis Chen curtis.chen@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
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