Change in coreboot[master]: mb/google/brya/var/primus: disabled autonomous GPIO power management

[Casper Chang (Code Review)]

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59079 )

Change subject: mb/google/brya/var/primus: disabled autonomous GPIO power management
......................................................................

mb/google/brya/var/primus: disabled autonomous GPIO power management

Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M

BUG=b:201054849
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.

Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58
---
M src/mainboard/google/brya/variants/primus/overridetree.cb
1 file changed, 10 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/59079/1

diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index c4debb4..81dc1c0 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -22,7 +22,16 @@
 end

chip soc/intel/alderlake
-
+	# This disabled autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
    register "SaGv" = "SaGv_Enabled"
    register "MaxDramSpeed" = "3733"