Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Enable SAR function

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23719

Change subject: mainboard/intel/cannonlake_rvp: Enable SAR function
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mainboard/intel/cannonlake_rvp: Enable SAR function

Change-Id: I23fc4d519376b2079bf95ae496903728adfdca96
Signed-off-by: Lijian Zhao 
---
M src/mainboard/intel/cannonlake_rvp/Kconfig
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
2 files changed, 12 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/23719/1

diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig
index fb6f9b1..622a2eb 100644
--- a/src/mainboard/intel/cannonlake_rvp/Kconfig
+++ b/src/mainboard/intel/cannonlake_rvp/Kconfig
@@ -79,4 +79,10 @@
 config VBOOT
    select VBOOT_LID_SWITCH
    select VBOOT_MOCK_SECDATA
+
+config CHROMEOS
+	select DSAR_ENABLE
+	select SAR_ENABLE
+	select USE_SAR
+
 endif
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 8502048..1e39253 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -77,7 +77,12 @@
    	device pci 12.6 off end # GSPI #2
    	device pci 14.0 on  end # USB xHCI
    	device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.3 on  end # CNVi wifi
+		device pci 14.3 on
+			chip drivers/intel/wifi
+				register "wake" = "GPE0_PME_B0"
+				device pci 00.0 on end
+			end
+		end # CNVi wifi
    	device pci 14.5 on  end # SDCard
    	device pci 15.0 on
    		chip drivers/i2c/hid