[S] Change in coreboot[main]: soc/amd/common/block/pci: Prevent disabling active bridges

[Patrick Rudolph (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune.

Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86216?usp=email )

Change subject: soc/amd/common/block/pci: Prevent disabling active bridges
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Patch Set 2:

(1 comment)

File src/soc/amd/common/block/pci/pcie_gpp.c:

https://review.coreboot.org/c/coreboot/+/86216/comment/3372a332_a7e2ba14?usp... :
PS1, Line 58: static void pcie_internal_gpp_enable(struct device *dev)
            : {
            : 	assert(dev->enabled);
            : 	if (!dev->enabled) {
            : 		/*
            : 		 * Cannot hide PPB devices! Must keep them enabled to
            : 		 * make sure PCI enumeration runs and avoids resource conflicts.
            : 		 */
            : 		dev->enabled = true;
            : 		dev->hidden = true;
            : 		dev->ops = &amd_pcie_disabled_gpp_ops;
            : 	}
            : }
> there are ways to hide the devices behind the bridges which fsp does; not 100% sure if it's the same […]

Done