[S] Change in coreboot[main]: vendorcode/amd/opensil: Implement cbmem_top_chipset

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76513?usp=email )

Change subject: vendorcode/amd/opensil: Implement cbmem_top_chipset
......................................................................

vendorcode/amd/opensil: Implement cbmem_top_chipset

Use an xPRF call to get the top of lower DRAM.

Organize Makefile to keep romstage/ramstage components separate.

Signed-off-by: Arthur Heymans 
Signed-off-by: Martin Roth 
Signed-off-by: Felix Held 
Change-Id: I269663414f4d8e39eb218cd6348bfce7989a79f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76513
Reviewed-by: Matt DeVillier 
Tested-by: build bot (Jenkins) 
Reviewed-by: Varshit Pandya 
---
M src/vendorcode/amd/opensil/genoa_poc/Makefile.inc
A src/vendorcode/amd/opensil/genoa_poc/romstage.c
2 files changed, 28 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Matt DeVillier: Looks good to me, approved
  Varshit Pandya: Looks good to me, approved

diff --git a/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc b/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc
index 5c7117a..c5742b5 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc
+++ b/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc
@@ -3,8 +3,12 @@
 CPPFLAGS_ramstage += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xUSL/FCH -I$(opensil_dir)/xUSL/FCH/Common -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF
 CPPFLAGS_romstage += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF

-ramstage-y += opensil_console.c
 romstage-y += opensil_console.c
+romstage-y += romstage.c
+
+ramstage-y += opensil_console.c

$(obj)/romstage/vendorcode/amd/opensil/genoa_poc/opensil_console.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
+$(obj)/romstage/vendorcode/amd/opensil/genoa_poc/romstage.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
+
 $(obj)/ramstage/vendorcode/amd/opensil/genoa_poc/opensil_console.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas
diff --git a/src/vendorcode/amd/opensil/genoa_poc/romstage.c b/src/vendorcode/amd/opensil/genoa_poc/romstage.c
new file mode 100644
index 0000000..e55ed1b
--- /dev/null
+++ b/src/vendorcode/amd/opensil/genoa_poc/romstage.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include "opensil_console.h"
+#include <xSIM-api.h>
+#include <xPRF-api.h>
+
+uintptr_t cbmem_top_chipset(void)
+{
+	SilDebugSetup(HostDebugService);
+	uintptr_t top_mem = xPrfGetLowUsableDramAddress(0);
+	printk(BIOS_DEBUG, "xPrfGetLowUsableDramAddress: 0x%lx\n", top_mem);
+
+	/* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size so
+	   account for potentially ill aligned TOP_MEM. */
+	if (CONFIG_SMM_TSEG_SIZE) {
+		top_mem -= CONFIG_SMM_TSEG_SIZE;
+		top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE);
+	}
+
+	return top_mem;
+}