[M] Change in coreboot[main]: soc/intel/xeon_sp/ibl: Update registers for reach bootable
Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84307?usp=email )
Change subject: soc/intel/xeon_sp/ibl: Update registers for reach bootable ......................................................................
soc/intel/xeon_sp/ibl: Update registers for reach bootable
Change-Id: Id2a2946b7fdfd7fd245835afe6abc9a3f7e1a508 Signed-off-by: Shuo Liu shuo.liu@intel.com Co-authored-by: Jincheng Li jincheng.li@intel.com --- M src/soc/intel/xeon_sp/ebg/include/soc/soc_pm.h M src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h M src/soc/intel/xeon_sp/ibl/include/soc/pmc.h M src/soc/intel/xeon_sp/ibl/include/soc/soc_pm.h M src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/lbg/include/soc/soc_pm.h 7 files changed, 37 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/84307/1
diff --git a/src/soc/intel/xeon_sp/ebg/include/soc/soc_pm.h b/src/soc/intel/xeon_sp/ebg/include/soc/soc_pm.h index d81bbf9..355c0c9 100644 --- a/src/soc/intel/xeon_sp/ebg/include/soc/soc_pm.h +++ b/src/soc/intel/xeon_sp/ebg/include/soc/soc_pm.h @@ -3,6 +3,9 @@ #ifndef _SOC_EBG_PM_H_ #define _SOC_EBG_PM_H_
+#define GPE_CNTL 0x42 +#define SWGPE_CTRL (1 << 1) + #define GPE0_STS(x) (0x60 + ((x) * 4)) #define GPE0_EN(x) (0x70 + ((x) * 4))
diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h index d8ee4e0..f4276c9 100644 --- a/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h @@ -3,16 +3,18 @@ #ifndef _PCR_IDS_H_ #define _PCR_IDS_H_
-#define PID_CSME0 0x90 -#define PID_ITSS 0xC4 -#define PID_RTC 0xC3 -#define PID_PSF3 0xBC -#define PID_DMI 0x88 -#define PID_GPIOCOM5 0x69 -#define PID_GPIOCOM4 0x6a -#define PID_GPIOCOM3 0x6b -#define PID_GPIOCOM2 0x6c -#define PID_GPIOCOM1 0x6d -#define PID_GPIOCOM0 0x6e +#define PID_NOT_SUPPORTED 0xff +#define PID_ITSS 0x00 +#define PID_IOTRAP 0x01 +#define PID_RTC PID_NOT_SUPPORTED +#define PID_DMI PID_NOT_SUPPORTED +#define PID_PSF3 PID_NOT_SUPPORTED +#define PID_ESPI 0x02 +#define PID_GPIOCOM0 0x03 +#define PID_GPIOCOM5 PID_NOT_SUPPORTED +#define PID_GPIOCOM4 PID_NOT_SUPPORTED +#define PID_GPIOCOM3 PID_NOT_SUPPORTED +#define PID_GPIOCOM2 PID_NOT_SUPPORTED +#define PID_GPIOCOM1 PID_NOT_SUPPORTED
#endif /* _PCR_IDS_H_ */ diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h b/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h index 59c2d73..09bfbdb 100644 --- a/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h @@ -36,7 +36,7 @@ #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE1 0x1928 #define ACTL 0x1BD8 -#define PMC_ACPI_CNT 0x1BD8 +#define PMC_ACPI_CNT 0x44 #define PWRM_EN (1 << 8) #define ACPI_EN (1 << 7) #define SCI_IRQ_SEL (7 << 0) diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/soc_pm.h b/src/soc/intel/xeon_sp/ibl/include/soc/soc_pm.h index 1cb36f4..9f6a3b0 100644 --- a/src/soc/intel/xeon_sp/ibl/include/soc/soc_pm.h +++ b/src/soc/intel/xeon_sp/ibl/include/soc/soc_pm.h @@ -3,8 +3,13 @@ #ifndef _SOC_IBL_PM_H_ #define _SOC_IBL_PM_H_
+#define GPE_CNTL 0x40 +#define SWGPE_CTRL (1 << 17) + #define GPE0_STS(x) (0x60 + ((x) * 4)) #define GPE0_EN(x) (0x70 + ((x) * 4)) +/* SWGPE_EN belongs to GPE0_EN(3) */ +#define SWGPE_EN (1 << 2)
/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */ #define ETR 0x1048 diff --git a/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h b/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h index 2f2f7d7..5518b59f 100644 --- a/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h +++ b/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h @@ -24,9 +24,15 @@ #define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) #define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2)
+#if CONFIG(SOC_INTEL_COMMON_IBL_BASE) +#define HPET_BUS_NUM 0x0 +#define HPET_DEV_NUM 0x1E +#define HPET0_FUNC_NUM 0x06 +#else #define HPET_BUS_NUM 0x0 #define HPET_DEV_NUM PCH_DEV_SLOT_LPC #define HPET0_FUNC_NUM 0x00 +#endif
#define PCH_DEV_SLOT_CSE 0x16 #define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) @@ -56,8 +62,14 @@ #define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) #define PCH_DEV_SPI _PCH_DEV(LPC, 5)
+#if CONFIG(SOC_INTEL_COMMON_IBL_BASE) +#define PCH_IOAPIC_BUS_NUMBER 0x0 +#define PCH_IOAPIC_DEV_NUM 0x1E +#define PCH_IOAPIC_FUNC_NUM 0x07 +#else #define PCH_IOAPIC_BUS_NUMBER 0xF0 #define PCH_IOAPIC_DEV_NUM 0x1F #define PCH_IOAPIC_FUNC_NUM 0x00 +#endif
#endif diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index bba0f2f..cd232bb 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -61,8 +61,6 @@ #define SMI_ON_SLP_EN_STS_BIT 4 #define LEGACY_USB_STS_BIT 3 #define BIOS_STS_BIT 2 -#define GPE_CNTL 0x42 -#define SWGPE_CTRL (1 << 1) #define DEVACT_STS 0x44 #define PM2_CNT 0x50 #define GPE0_REG_MAX 4 diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pm.h b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pm.h index 2e309b5..bdac096 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pm.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pm.h @@ -3,6 +3,9 @@ #ifndef _SOC_LBG_PM_H_ #define _SOC_LBG_PM_H_
+#define GPE_CNTL 0x42 +#define SWGPE_CTRL (1 << 1) + #define GPE0_STS(x) (0x80 + ((x) * 4)) #define GPE0_EN(x) (0x90 + ((x) * 4))
-
Shuo Liu (Code Review)