Change in ...coreboot[master]: nb/intel/gm45: Correctly cache TSEG

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29866

Change subject: nb/intel/gm45: Correctly cache TSEG
......................................................................

nb/intel/gm45: Correctly cache TSEG

Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/gm45/ram_calc.c
2 files changed, 16 insertions(+), 21 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29866/1

diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 0fd7fe5..a001a67 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -221,22 +221,6 @@
    return NULL;
 }

-u32 northbridge_get_tseg_base(void)
-{
-	return (u32)smm_region_start();
-}
-
-u32 northbridge_get_tseg_size(void)
-{
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-
-	if (dev == NULL)
-		die("could not find pci 00:00.0!\n");
-
-	const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);
-	return decode_tseg_size(esmramc) << 10;
-}
-
 void northbridge_write_smram(u8 smram)
 {
    struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 5af3e16..da1963e 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -106,6 +106,17 @@
    return tor;
 }

+u32 northbridge_get_tseg_base(void)
+{
+	return (u32)smm_region_start();
+}
+
+u32 northbridge_get_tseg_size(void)
+{
+	const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
+	return decode_tseg_size(esmramc) << 10;
+}
+
 /* Depending of UMA and TSEG configuration, TSEG might start at any
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
@@ -135,12 +146,12 @@
    /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
    postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);

-	/* Cache a 8 MiB region below the top of ram and 8 MiB above top of
+	/* Cache 8 MiB region below the top of ram and 2 MiB above top of
     * ram to cover both cbmem as the TSEG region.
-	 */
-	top_of_ram = (uintptr_t)cbmem_top();
-	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
-			MTRR_TYPE_WRBACK);
+	 */	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
+			       MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
+			       northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);

run_postcar_phase(&pcf);