New patch to review for coreboot: aec67ba amd/car/post_cache_as_ram: Switch stack in assembly rather than in C

[Vladimir Serbinenko]

Vladimir Serbinenko ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4286

-gerrit

commit aec67ba8f659dfb818af9c5999cf8bfa1f9db206
Author: Vladimir Serbinenko 
Date:   Tue Nov 26 17:49:29 2013 +0100

amd/car/post_cache_as_ram: Switch stack in assembly rather than in C

Compiler may do loads of optimisations around stack switch and so it's allowed
    to break stack switch as it sees fit. Do it in assembly instead.

Not tested.

Change-Id: I277a62a9052e8fe9b04e7c65d149e087282ac2a2
    Signed-off-by: Vladimir Serbinenko 
---
 src/cpu/amd/car/cache_as_ram.inc    |  7 +++++++
 src/cpu/amd/car/post_cache_as_ram.c | 20 ++++++++------------
 2 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 7070cf9..199083b 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -414,10 +414,17 @@ CAR_FAM10_ap_out:
    pushl	%ebx		/* Init detected. */
    pushl	%eax		/* BIST */
    call	cache_as_ram_main
+
    /* We will not go back. */

post_code(0xaf)		/* Should never see this POST code. */

+	.globl cache_as_ram_switch_stack
+
+cache_as_ram_switch_stack:
+	subl	$(( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )), %esp
+	call	cache_as_ram_new_stack
+
 all_mtrr_msrs:
    /* fixed MTRR MSRs */
    .long	MTRRfix64K_00000_MSR
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index eca7673..1d0ba7c 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -75,6 +75,8 @@ static void vErrata343(void)
 #endif
 }

+void cache_as_ram_switch_stack(void);
+
 static void post_cache_as_ram(void)
 {
 #if CONFIG_HAVE_ACPI_RESUME
@@ -92,9 +94,6 @@ static void post_cache_as_ram(void)
    }
 #endif

-	unsigned testx = 0x5a5a5a5a;
-	print_debug_pcar("testx = ", testx);
-
    /* copy data from cache as ram to
    	ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
     */
@@ -112,21 +111,18 @@ static void post_cache_as_ram(void)
    vErrata343();

memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
+}

-	__asm__ volatile (
-		/* set new esp */ /* before CONFIG_RAMBASE */
-		"subl   %0, %%esp\n\t"
-		::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
-		/* discard all registers (eax is used for %0), so gcc redoes everything
-		   after the stack is moved */
-		: "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp"
-	);
+void
+cache_as_ram_new_stack (void);

+void
+cache_as_ram_new_stack (void)
+{
    /* We can put data to stack again */

/* only global variable sysinfo in cache need to be offset */
    print_debug("Done\n");
-	print_debug_pcar("testx = ", testx);

print_debug("Disabling cache as ram now \n");