[XS] Change in coreboot[main]: mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3

[John Su (Code Review)]

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86362?usp=email )

Change subject: mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3
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mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3

Remove GPP_E13 from being used as RAM ID3.
Planned to be used as a strap pin to disable memory channels
for x32 memory configuration.

BUG=b:379311559
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I418f84255959452d5a63612ab703ec11d81f2e33
Signed-off-by: John Su 
---
M src/mainboard/google/brya/variants/uldrenite/gpio.c
M src/mainboard/google/brya/variants/uldrenite/memory.c
2 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/86362/1

diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index 4b900fb..f926e3a 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -184,7 +184,7 @@
    PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
    /* E12 : THC0_SPI1_IO1 ==> RAM_ID2 */
    PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG),
-	/* E13 : NC ==> RAM_ID3 */
+	/* E13 : NC ==> GPP_E13_STRAP */
    PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
    /* E14 : DDSP_HPDA ==> EDP_HPD */
    PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
@@ -418,6 +418,8 @@
    PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
    /* E3 : PROC_GP0 ==> SOC_WP_OD */
    PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),
+	/* E13 : NC ==> GPP_E13_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
    /* F12 : NC ==> WWAN_RST_L */
    PAD_CFG_GPO(GPP_F12, 0, DEEP),
    /* F13 : NC ==> PLTRST_WWAN# */
diff --git a/src/mainboard/google/brya/variants/uldrenite/memory.c b/src/mainboard/google/brya/variants/uldrenite/memory.c
index 03e97a1..9ade7c2 100644
--- a/src/mainboard/google/brya/variants/uldrenite/memory.c
+++ b/src/mainboard/google/brya/variants/uldrenite/memory.c
@@ -81,13 +81,11 @@
     * GPIO_MEM_CONFIG_0	GPP_E2
     * GPIO_MEM_CONFIG_1	GPP_E1
     * GPIO_MEM_CONFIG_2	GPP_E12
-	 * GPIO_MEM_CONFIG_3	GPP_E13
     */
    gpio_t spd_gpios[] = {
    	GPP_E2,
    	GPP_E1,
-		GPP_E12,
-		GPP_E13
+		GPP_E12
    };

return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));