[S] Change in coreboot[master]: spd/lp5: Modify Hynix H58G66BK8BX067 Speed

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Frank Wu, John Su, Dtrain Hsu, Subrata Banik, Eric Lai, Martin Roth.

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73251 )

Change subject: spd/lp5: Modify Hynix H58G66BK8BX067 Speed
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Patch Set 1:

(1 comment)

File spd/lp5/memory_parts.json:

https://review.coreboot.org/c/coreboot/+/73251/comment/5161cec7_390e46e7 
PS1, Line 207:                 "speedMbps": 8533,
Looking at the next CL, it seems this memory part is used only in Markarth. If so, this memory speed bump is not required.

Even though the SPD tool generates the required speed, unfortunately memory training code for Mendocino SoC limits the speed to 5500 MT/s. So this change does not take any effect in Markarth.