Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40035 )
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
soc/intel/xeon_sp/cpx: Add multi-core init
Add minimal MP init. No SMM, no turbo, not c/p states.
TEST=boot linux kernel, observe CPUs are online, schedule tasks and perform useful work. Tested on Cedar Island CRB with only 1 socket populated
Change-Id: I0af374ab3956009e9208917d911d29eb21db6069 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/chip.c A src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 5 files changed, 102 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40035/1
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b909a45..e00ae40 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -8,9 +8,10 @@ subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc +subdirs-y += ../../../../cpu/intel/microcode
romstage-y += romstage.c -ramstage-y += chip.c acpi.c +ramstage-y += chip.c acpi.c cpu.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx
diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 48ad374..9955e2b 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -10,6 +10,7 @@ #include <cpu/x86/smm.h> #include <device/pci.h> #include <intelblocks/acpi.h> +#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/nvs.h> #include <soc/pm.h> diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index dbbf3b3..748e114 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */
+#include <arch/acpigen.h> #include <arch/ioapic.h> #include <cbfs.h> #include <console/console.h> @@ -10,6 +11,8 @@ #include <soc/ramstage.h> #include <soc/pm.h>
+void cpx_init_cpus(struct device *dev); + /* C620 IOAPIC has 120 redirection entries */ #define C620_IOAPIC_REDIR_ENTRIES 120
@@ -29,16 +32,11 @@ .scan_bus = &pci_domain_scan_bus, };
-static void init_cpus(struct device *dev) -{ - /* not implemented yet */ -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = init_cpus, + .init = cpx_init_cpus, .scan_bus = NULL, };
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c new file mode 100644 index 0000000..1ea59bd --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/acpigen.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/mtrr.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/mp_init.h> +#include <soc/cpu.h> + +static const void* microcode_patch; + +void get_microcode_info(const void **microcode, int *parallel) +{ + *microcode = intel_mp_current_microcode(); + *parallel = 1; +} + +const void *intel_mp_current_microcode(void) +{ + return microcode_patch; +} + +static void each_cpu_init(struct device *cpu) +{ + printk(BIOS_INFO, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); + + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = each_cpu_init, +}; + +static const struct cpu_device_id cpu_table[] = { + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0}, + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + +/* + * Do essential initialization tasks before APs can be fired up + */ +static void pre_mp_init(void) +{ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_thread_count(void) +{ + unsigned int num_phys = 0, num_virts = 0; + + cpu_read_topology(&num_phys, &num_virts); + return num_virts; +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_thread_count, + .get_microcode_info = get_microcode_info +}; + +void cpx_init_cpus(struct device *dev) +{ + microcode_patch = intel_microcode_find(); + + if (!microcode_patch) + printk(BIOS_ERR, "microcode not found in CBFS!\n"); + + intel_microcode_load_unlocked(microcode_patch); + + if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + printk(BIOS_ERR, "MP initialization failure.\n"); +} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index f33df89..563270d 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -1,4 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */
-/* nothing here yet */ +#ifndef _SOC_CPU_H +#define _SOC_CPU_H + +#include <device/device.h> + +#define CPUID_COOPERLAKE_SP_A0 0x05065a + +void cpx_init_cpus(struct device *dev); + +#endif
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40035 )
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40035/1/src/soc/intel/xeon_sp/cpx/c... File src/soc/intel/xeon_sp/cpx/cpu.c:
https://review.coreboot.org/c/coreboot/+/40035/1/src/soc/intel/xeon_sp/cpx/c... PS1, Line 16: static const void* microcode_patch; "foo* bar" should be "foo *bar"
Hello Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40035
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
soc/intel/xeon_sp/cpx: Add multi-core init
Add minimal MP init. No SMM, no turbo, not c/p states.
TEST=boot linux kernel, observe CPUs are online, schedule tasks and perform useful work. Tested on Cedar Island CRB with only 1 socket populated
Change-Id: I0af374ab3956009e9208917d911d29eb21db6069 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/chip.c A src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 5 files changed, 102 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40035/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40035
to look at the new patch set (#3).
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
soc/intel/xeon_sp/cpx: Add multi-core init
Add minimal MP init. No SMM, no turbo, not c/p states.
TEST=boot linux kernel, observe CPUs are online, schedule tasks and perform useful work. Tested on Cedar Island CRB with only 1 socket populated
Change-Id: I0af374ab3956009e9208917d911d29eb21db6069 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/chip.c A src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 4 files changed, 101 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40035/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40035 )
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40035/3/src/soc/intel/xeon_sp/cpx/c... File src/soc/intel/xeon_sp/cpx/cpu.c:
https://review.coreboot.org/c/coreboot/+/40035/3/src/soc/intel/xeon_sp/cpx/c... PS3, Line 16: static const void* microcode_patch; "foo* bar" should be "foo *bar"
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40035
to look at the new patch set (#4).
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
soc/intel/xeon_sp/cpx: Add multi-core init
Add minimal MP init. No SMM, no turbo, not c/p states.
TEST=boot linux kernel, observe CPUs are online, schedule tasks and perform useful work. Tested on Cedar Island CRB with only 1 socket populated
Change-Id: I0af374ab3956009e9208917d911d29eb21db6069 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/chip.c A src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 4 files changed, 99 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40035/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40035 )
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40035/4/src/soc/intel/xeon_sp/cpx/c... File src/soc/intel/xeon_sp/cpx/cpu.c:
https://review.coreboot.org/c/coreboot/+/40035/4/src/soc/intel/xeon_sp/cpx/c... PS4, Line 16: static const void* microcode_patch; "foo* bar" should be "foo *bar"
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40035
to look at the new patch set (#5).
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
soc/intel/xeon_sp/cpx: Add multi-core init
Add minimal MP init. No SMM, no turbo, not c/p states.
TEST=boot linux kernel, observe CPUs are online, schedule tasks and perform useful work. Tested on Cedar Island CRB with only 1 socket populated
Change-Id: I0af374ab3956009e9208917d911d29eb21db6069 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/chip.c A src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 4 files changed, 99 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40035/5
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40035
to look at the new patch set (#6).
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
soc/intel/xeon_sp/cpx: Add multi-core init
Add minimal MP init. No SMM, no turbo, not c/p states.
TEST=boot linux kernel, observe CPUs are online, schedule tasks and perform useful work. Tested on Cedar Island CRB with only 1 socket populated
Change-Id: I0af374ab3956009e9208917d911d29eb21db6069 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/chip.c A src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 4 files changed, 100 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40035/6
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40035 )
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
Patch Set 6: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/40035/6/src/soc/intel/xeon_sp/cpx/c... File src/soc/intel/xeon_sp/cpx/chip.c:
https://review.coreboot.org/c/coreboot/+/40035/6/src/soc/intel/xeon_sp/cpx/c... PS6, Line 4: #include <arch/acpigen.h> Is this inclusion really necessary?
https://review.coreboot.org/c/coreboot/+/40035/6/src/soc/intel/xeon_sp/cpx/c... File src/soc/intel/xeon_sp/cpx/cpu.c:
https://review.coreboot.org/c/coreboot/+/40035/6/src/soc/intel/xeon_sp/cpx/c... PS6, Line 64: cpu_read_topology(&num_phys, &num_virts); Please add debug information about the number of threads and cores, as is done for other processors: https://github.com/coreboot/coreboot/blob/bf48f6ab1127f3ba6a592f17ec49255f3e...
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40035
to look at the new patch set (#7).
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
soc/intel/xeon_sp/cpx: Add multi-core init
Add minimal MP init. No SMM, no turbo, not c/p states.
TEST=boot linux kernel, observe CPUs are online, schedule tasks and perform useful work. Tested on Cedar Island CRB with only 1 socket populated
Change-Id: I0af374ab3956009e9208917d911d29eb21db6069 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/chip.c A src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 4 files changed, 100 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40035/7
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40035 )
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40035/6/src/soc/intel/xeon_sp/cpx/c... File src/soc/intel/xeon_sp/cpx/chip.c:
https://review.coreboot.org/c/coreboot/+/40035/6/src/soc/intel/xeon_sp/cpx/c... PS6, Line 4: #include <arch/acpigen.h>
Is this inclusion really necessary?
nope. addressed, thanks
https://review.coreboot.org/c/coreboot/+/40035/6/src/soc/intel/xeon_sp/cpx/c... File src/soc/intel/xeon_sp/cpx/cpu.c:
https://review.coreboot.org/c/coreboot/+/40035/6/src/soc/intel/xeon_sp/cpx/c... PS6, Line 64: cpu_read_topology(&num_phys, &num_virts);
Please add debug information about the number of threads and cores, as is done for other processors: […]
Done
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40035 )
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
Patch Set 7: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/40035/7/src/soc/intel/xeon_sp/cpx/c... File src/soc/intel/xeon_sp/cpx/cpu.c:
https://review.coreboot.org/c/coreboot/+/40035/7/src/soc/intel/xeon_sp/cpx/c... PS7, Line 82: intel_microcode_load_unlocked According to the BWG, the cache should be disabled before we update the microcode (Phase 1). Are you sure the cache is disabled now?
I see that this will be done in commit_var_mtrrs () (which is called in x86_setup_mtrrs_with_detect): https://github.com/coreboot/coreboot/blob/9890bd98b07c83c0e346fbb6f8284176e8...
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40035 )
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40035/7/src/soc/intel/xeon_sp/cpx/c... File src/soc/intel/xeon_sp/cpx/cpu.c:
https://review.coreboot.org/c/coreboot/+/40035/7/src/soc/intel/xeon_sp/cpx/c... PS7, Line 82: intel_microcode_load_unlocked
According to the BWG, the cache should be disabled before we update the microcode (Phase 1). […]
yeah this is a valid concern. However I believe this "phase 1" is taking place in FSP-T. so we should be good at this point.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40035 )
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/40035/7/src/soc/intel/xeon_sp/cpx/c... File src/soc/intel/xeon_sp/cpx/cpu.c:
https://review.coreboot.org/c/coreboot/+/40035/7/src/soc/intel/xeon_sp/cpx/c... PS7, Line 82: intel_microcode_load_unlocked
yeah this is a valid concern. However I believe this "phase 1" is taking place in FSP-T. […]
Well, however, we have to be careful with cache manipulations, since functions from the common cpu initialization code may not take into account the specifics of the CPX + fsp platform and use the cache incorrectly.
Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40035 )
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
soc/intel/xeon_sp/cpx: Add multi-core init
Add minimal MP init. No SMM, no turbo, not c/p states.
TEST=boot linux kernel, observe CPUs are online, schedule tasks and perform useful work. Tested on Cedar Island CRB with only 1 socket populated
Change-Id: I0af374ab3956009e9208917d911d29eb21db6069 Signed-off-by: Andrey Petrov anpetrov@fb.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40035 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/chip.c A src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 4 files changed, 100 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b909a45..e00ae40 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -8,9 +8,10 @@ subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc +subdirs-y += ../../../../cpu/intel/microcode
romstage-y += romstage.c -ramstage-y += chip.c acpi.c +ramstage-y += chip.c acpi.c cpu.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index dbbf3b3..e4063dc 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -7,6 +7,7 @@ #include <cpu/x86/lapic.h> #include <device/pci.h> #include <fsp/api.h> +#include <soc/cpu.h> #include <soc/ramstage.h> #include <soc/pm.h>
@@ -29,16 +30,11 @@ .scan_bus = &pci_domain_scan_bus, };
-static void init_cpus(struct device *dev) -{ - /* not implemented yet */ -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = init_cpus, + .init = cpx_init_cpus, .scan_bus = NULL, };
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c new file mode 100644 index 0000000..8824686 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/acpigen.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/mtrr.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/mp_init.h> +#include <soc/cpu.h> + +static const void *microcode_patch; + +void get_microcode_info(const void **microcode, int *parallel) +{ + *microcode = intel_mp_current_microcode(); + *parallel = 1; +} + +const void *intel_mp_current_microcode(void) +{ + return microcode_patch; +} + +static void each_cpu_init(struct device *cpu) +{ + printk(BIOS_INFO, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); + + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = each_cpu_init, +}; + +static const struct cpu_device_id cpu_table[] = { + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0}, + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + +/* + * Do essential initialization tasks before APs can be fired up + */ +static void pre_mp_init(void) +{ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_thread_count(void) +{ + unsigned int num_phys = 0, num_virts = 0; + + cpu_read_topology(&num_phys, &num_virts); + printk(BIOS_SPEW, "Detected %u cores and %u threads\n", num_phys, num_virts); + return num_virts; +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_thread_count, + .get_microcode_info = get_microcode_info +}; + +void cpx_init_cpus(struct device *dev) +{ + microcode_patch = intel_microcode_find(); + + if (!microcode_patch) + printk(BIOS_ERR, "microcode not found in CBFS!\n"); + + intel_microcode_load_unlocked(microcode_patch); + + if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + printk(BIOS_ERR, "MP initialization failure.\n"); +} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index f33df89..563270d 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -1,4 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */
-/* nothing here yet */ +#ifndef _SOC_CPU_H +#define _SOC_CPU_H + +#include <device/device.h> + +#define CPUID_COOPERLAKE_SP_A0 0x05065a + +void cpx_init_cpus(struct device *dev); + +#endif
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40035 )
Change subject: soc/intel/xeon_sp/cpx: Add multi-core init ......................................................................
Patch Set 8:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2036 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2035 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2034
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Andrey Petrov (Code Review)
-
build bot (Jenkins) (Code Review)
-
Maxim Polyakov (Code Review)