Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27584
Change subject: cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSx ......................................................................
cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSx
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures Software Developer’s Manual.
The purpose is to differentiate with MSR_SMRR_PHYSx.
Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/cpu/x86/mtrr.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/skylake/smmrelocate.c 12 files changed, 24 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/27584/1
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 9ff1e55..55d34a0 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -70,8 +70,8 @@ { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask); }
static inline void write_emrr(struct smm_relocation_params *relo_params) diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index e80fa31..e3cb11b 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -61,8 +61,8 @@ { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask); }
/* The relocation work is actually performed in SMM context, but the code diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index f52a77b..58a3ce5 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -28,8 +28,8 @@ #define MTRR_DEF_TYPE_FIX_EN (1 << 10)
-#define SMRR_PHYS_BASE 0x1f2 -#define SMRR_PHYS_MASK 0x1f3 +#define IA32_SMRR_PHYSBASE 0x1f2 +#define IA32_SMRR_PHYSMASK 0x1f3
#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 6905894..1367160 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -223,10 +223,10 @@ /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRR_PHYS_BASE, smrr); + wrmsr(IA32_SMRR_PHYSBASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYSMASK, smrr); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; } diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 77d2dda..ea299ce 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -179,10 +179,10 @@ /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRR_PHYS_BASE, smrr); + wrmsr(IA32_SMRR_PHYSBASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYSMASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 31b1b78..17aa36a 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -195,10 +195,10 @@ /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRR_PHYS_BASE, smrr); + wrmsr(IA32_SMRR_PHYSBASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYSMASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 2d90ebc..e9a215c 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -38,8 +38,8 @@ { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask); }
static inline void write_emrr(struct smm_relocation_params *relo_params) diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 3c60ef2..9e89265 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -41,8 +41,8 @@ { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask); }
static void update_save_state(int cpu, uintptr_t curr_smbase, diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index d486435..815bd46 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -80,10 +80,10 @@ /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRR_PHYS_BASE, smrr); + wrmsr(IA32_SMRR_PHYSBASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYSMASK, smrr); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; } diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index c7694b9..44cd403 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -139,10 +139,10 @@ /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRR_PHYS_BASE, smrr); + wrmsr(IA32_SMRR_PHYSBASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRR_PHYS_MASK, smrr); + wrmsr(IA32_SMRR_PHYSMASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c index 28bc8c9..a0f3e5a 100644 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c @@ -39,8 +39,8 @@ { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask); }
static inline void write_prmrr(struct smm_relocation_params *relo_params) diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 6a8e64b..800811a 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -41,8 +41,8 @@ { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask); }
static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
-
Arthur Heymans (Code Review)