Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skylake/vr_config: Add VR config for Skylake S ......................................................................
soc/skylake/vr_config: Add VR config for Skylake S
These changes are in accordance with the documentation: [*] page 112-119, 6th Generation Intel(R) Processor Families for S-Platforms, Volume 1 of 2, Datasheet, August 2018. Document Number: 332687-008EN
Tested on Asrock H110M DVS with i5-6600 (4 cores) CPU
Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/vr_config.c 1 file changed, 42 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35167/1
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index fc48558..82f3fdc 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -113,28 +113,37 @@ * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the * Iccmax is the same among KBL-Y but KBL-U/R. * Addendum for AML-Y #594883, IccMax for IA core is 28A. - * KBL-S #335195, KBL-H #335190 - * +----------------+-------------+---------------+------+-----+ - * | Domain/Setting | SA | IA | GTUS | GTS | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-S) | 11.1A | 100A | 48A | 48A | - * | | | ... | 45A | 45A | - * | | | 40A | 35A | 35A | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-H) | 11.1A (45W) | 68A | 55A | 55A | - * | | 6.6A (18W) | 60A | | | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | - * | | 4.5A(Others)| 29A(P/C) | | | - * | | | 32A(i3/i5) | | | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ + * KBL-S #335195, KBL-H #335190, SKL-S #332687 + * +---------------------+-------------+-------+------+------+-----+ + * | Domain/Setting | Cores/TDP | SA | IA | GTUS | GTS | + * +---------------------+-------------+-------+------+------+-----+ + * | IccMax(KBL-S/SKL-S) | 4C/91W | 11.1A | 100A | 45A | 45A | + * | | 4C/80W * | | 82A | | | + * | | 4C/65W | | 79A | | | + * | | 4C/45W * | | 70A | 35A | 35A | + * | | 4C/35W | | 66A | | | + * | | 4C/25W * | | 55A | | | + * | | 2C/54W | | 58A | 48A | 48A | + * | | 2C/51W | | 45A | | | + * | | 2C/35W | | 40A | | | + * +---------------------+-------------+-------+------+------+-----+ + * | IccMax(KBL-H) | 4C/45W | 11.1A | 68A | 55A | 55A | + * | | 4C/18W | 6.6A | 60A | | | + * +---------------------+-------------+-------+------+------+-----+ + * | IccMax(KBL-U/R) | 4C/15W (U42)| 6A | 64A | 31A | 31A | + * | | 2C/15W (P/C)| 4.5A | 29A | | | + * | | 2C/28W (OPC)| | 32A | | | + * +---------------------+-------------+-------+------+------+-----+ + * | IccMax(KBL-Y) | 2C/4.5W | 4.1A | 24A | 24A | 24A | + * | | 2C/6W | | | | | + * +---------------------+-------------+-------+------+------+-----+ + * | IccMax(AML-Y) | 2C/5W | 4.1A | 28A | 24A | 24A | + * +---------------------+-------------+-------+------+------+-----+ + * [*] - for Skylake only */
switch (mch_id) { + case PCI_DEVICE_ID_INTEL_SKL_ID_S_2: case PCI_DEVICE_ID_INTEL_KBL_ID_S: { uint16_t icc_max[NUM_VR_DOMAINS] = { VR_CFG_AMP(11.1), @@ -148,21 +157,28 @@ icc_max[VR_IA_CORE] = VR_CFG_AMP(45);
return icc_max[domain]; - } + case PCI_DEVICE_ID_INTEL_SKL_ID_S_4: case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_DT: { uint16_t icc_max[NUM_VR_DOMAINS] = { VR_CFG_AMP(11.1), - VR_CFG_AMP(66), + VR_CFG_AMP(55), VR_CFG_AMP(45), VR_CFG_AMP(45), }; if (tdp >= 91) icc_max[VR_IA_CORE] = VR_CFG_AMP(100); + else if (tdp >= 80) + icc_max[VR_IA_CORE] = VR_CFG_AMP(82); else if (tdp >= 65) icc_max[VR_IA_CORE] = VR_CFG_AMP(79); - else if (tdp >= 35) { + else if (tdp >= 45) + icc_max[VR_IA_CORE] = VR_CFG_AMP(70); + else if (tdp >= 25) { + if (tdp >= 35) + icc_max[VR_IA_CORE] = VR_CFG_AMP(66); + icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(35); icc_max[VR_GT_SLICED] = VR_CFG_AMP(35); } @@ -241,8 +257,10 @@ }
switch (mch_id) { - case PCI_DEVICE_ID_INTEL_KBL_ID_S: /* fallthrough */ - case PCI_DEVICE_ID_INTEL_KBL_ID_DT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_S_2: + case PCI_DEVICE_ID_INTEL_SKL_ID_S_4: + case PCI_DEVICE_ID_INTEL_KBL_ID_S: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_DT: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: { static const uint16_t loadline[NUM_VR_DOMAINS] = { VR_CFG_MOHMS(0), /* Not specified */
Hello Patrick Rudolph, Angel Pons, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35167
to look at the new patch set (#2).
Change subject: soc/skylake/vr_config: Add VR config for Skylake S ......................................................................
soc/skylake/vr_config: Add VR config for Skylake S
These changes are in accordance with the documentation: [*] page 112-119, 6th Generation Intel(R) Processor Families for S-Platforms, Volume 1 of 2, Datasheet, August 2018. Document Number: 332687-008EN
Tested on Asrock H110M DVS with i5-6600 (4 cores) CPU
Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/vr_config.c 1 file changed, 42 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35167/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skylake/vr_config: Add VR config for Skylake S ......................................................................
Patch Set 2:
(1 comment)
Maybe making a table (2D array) with the IccMax values would be better to avoid confusion
https://review.coreboot.org/c/coreboot/+/35167/2/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/2/src/soc/intel/skylake/vr_co... PS2, Line 176: else if (tdp >= 45) : icc_max[VR_IA_CORE] = VR_CFG_AMP(70); GT_UNSLICED and GT_SLICED don't get the IccMax of 35A configured, which they should according to the table above
Hello Patrick Rudolph, Angel Pons, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35167
to look at the new patch set (#3).
Change subject: soc/skylake/vr_config: Add VR config for Skylake S ......................................................................
soc/skylake/vr_config: Add VR config for Skylake S
These changes are in accordance with the documentation: [*] page 112-119, 6th Generation Intel(R) Processor Families for S-Platforms, Volume 1 of 2, Datasheet, August 2018. Document Number: 332687-008EN
Tested on Asrock H110M DVS with i5-6600 (4 cores) CPU
Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/vr_config.c 1 file changed, 42 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35167/3
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skylake/vr_config: Add VR config for Skylake S ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35167/2/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/2/src/soc/intel/skylake/vr_co... PS2, Line 176: else if (tdp >= 45) : icc_max[VR_IA_CORE] = VR_CFG_AMP(70);
GT_UNSLICED and GT_SLICED don't get the IccMax of 35A configured, which they should according to the […]
if I'm not mistaken, then this isn't in the documentation. The Iccmax_GT for 45 watts is missed. I think it would be better to set the smallest limit 35A, the same as for 35 watts. And also, add a comment about this. Do you agree?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skylake/vr_config: Add VR config for Skylake S ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35167/2/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/2/src/soc/intel/skylake/vr_co... PS2, Line 176: else if (tdp >= 45) : icc_max[VR_IA_CORE] = VR_CFG_AMP(70);
if I'm not mistaken, then this isn't in the documentation. The Iccmax_GT for 45 watts is missed. […]
SKL-H values appear on a different document: #332986
I made a table for Skylake:
Segment IA GT (GT/GTx) SA -------------------------------------------- S (95W) quad 100 45 11.1 S (80W) quad 82 45 11.1 S (65W) quad 79 45 11.1 S (45W) quad 70 0 11.1 S (35W) quad 66 35 11.1 S (25W) quad 55 35 11.1
S (54W) dual 58 48 11.1 S (51W) dual 45 48 11.1 S (35W) dual 40 48 11.1
H (65W) GT4 74 105/24 8 H (45W) GT4 74 94/20 8 H (45W) GT2 68 55 11.1 H (35W) GT4 66 94/20 8 H (35W) GT2 60 55 11.1
U (28W) GT3 32 57/19 5.1 U (15W) GT3 29 57/19 5.1 U (15W) GT2 29 31 4.5
Y (6W) 24 24 4.1 Y (4.5W) 24 24 4.1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skylake/vr_config: Add VR config for Skylake S ......................................................................
Patch Set 3: Code-Review-1
-1 as it would cause problems with FSP 1.1 getting wrong IccMax values.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skylake/vr_config: Add VR config for Skylake S ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35167/3/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/3/src/soc/intel/skylake/vr_co... PS3, Line 148: uint16_t icc_max[NUM_VR_DOMAINS] = { : VR_CFG_AMP(11.1), : VR_CFG_AMP(40), : VR_CFG_AMP(48), : VR_CFG_AMP(48), : }; Specifically, NUM_VR_DOMAINS = 5 for FSP 1.1, and the extra element (VR_RING) is in the middle, so values would get mixed up...
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skylake/vr_config: Add VR config for Skylake S ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35167/3/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/3/src/soc/intel/skylake/vr_co... PS3, Line 148: uint16_t icc_max[NUM_VR_DOMAINS] = { : VR_CFG_AMP(11.1), : VR_CFG_AMP(40), : VR_CFG_AMP(48), : VR_CFG_AMP(48), : };
Specifically, NUM_VR_DOMAINS = 5 for FSP 1. […]
Right. In the original platform support only devicetree values were used, thus this code was never run. Looking at the FSP documentation I can't even tell if FSP2.0 uses 4 or 5 VR_DOMAINS for SKL. I'd guess 5 as the register takes 5 values at maximum.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skylake/vr_config: Add VR config for Skylake S ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35167/3/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/3/src/soc/intel/skylake/vr_co... PS3, Line 148: uint16_t icc_max[NUM_VR_DOMAINS] = { : VR_CFG_AMP(11.1), : VR_CFG_AMP(40), : VR_CFG_AMP(48), : VR_CFG_AMP(48), : };
Right. […]
FSP 1.1 takes 5 values, FSP 2.0 takes 4 values. I made this earlier: http://dpaste.com/29MBM4R
Using a few larger tables (maybe a table per "series" (S-series, U-series, Y-series...) would make sense. I have to think it through, though.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skylake/vr_config: Add VR config for Skylake S ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35167/3/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/3/src/soc/intel/skylake/vr_co... PS3, Line 148: uint16_t icc_max[NUM_VR_DOMAINS] = { : VR_CFG_AMP(11.1), : VR_CFG_AMP(40), : VR_CFG_AMP(48), : VR_CFG_AMP(48), : };
FSP 1.1 takes 5 values, FSP 2.0 takes 4 values. I made this earlier: http://dpaste.com/29MBM4R […]
Hmm, excuse me, but where are the Iccmax for the VR_RING domain? I see in the device tree for some boards that these values are the same as in the VR_IA_CORE domain?
Hello Patrick Rudolph, Angel Pons, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35167
to look at the new patch set (#4).
Change subject: [WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U ......................................................................
[WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U
These changes are in accordance with the documentation:
[*] S-Platforms, Document Number: 332687-008EN [*] H-Platforms, Document Number: 332986-010EN [*] U/Y-Platforms, Document Number: 332990-008EN
Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/vr_config.c 1 file changed, 81 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35167/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: [WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35167/4/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/4/src/soc/intel/skylake/vr_co... PS4, Line 191: else if (tdp >= 25) { else should follow close brace '}'
https://review.coreboot.org/c/coreboot/+/35167/4/src/soc/intel/skylake/vr_co... PS4, Line 217: case PCI_DEVICE_ID_INTEL_SKL_ID_H_2: Possible switch case/default not preceded by break or fallthrough comment
https://review.coreboot.org/c/coreboot/+/35167/4/src/soc/intel/skylake/vr_co... PS4, Line 218: case PCI_DEVICE_ID_INTEL_SKL_ID_H_EM: Possible switch case/default not preceded by break or fallthrough comment
Hello Patrick Rudolph, Angel Pons, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35167
to look at the new patch set (#5).
Change subject: [WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U ......................................................................
[WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U
These changes are in accordance with the documentation:
[*] S-Platforms, Document Number: 332687-008EN [*] H-Platforms, Document Number: 332986-010EN [*] U/Y-Platforms, Document Number: 332990-008EN
Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/vr_config.c 1 file changed, 82 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35167/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: [WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35167/5/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/5/src/soc/intel/skylake/vr_co... PS5, Line 191: else if (tdp >= 25) { else should follow close brace '}'
https://review.coreboot.org/c/coreboot/+/35167/5/src/soc/intel/skylake/vr_co... PS5, Line 216: case PCI_DEVICE_ID_INTEL_SKL_ID_H_2: Possible switch case/default not preceded by break or fallthrough comment
https://review.coreboot.org/c/coreboot/+/35167/5/src/soc/intel/skylake/vr_co... PS5, Line 217: case PCI_DEVICE_ID_INTEL_SKL_ID_H_EM: Possible switch case/default not preceded by break or fallthrough comment
https://review.coreboot.org/c/coreboot/+/35167/5/src/soc/intel/skylake/vr_co... PS5, Line 218: case PCI_DEVICE_ID_INTEL_KBL_ID_H: Possible switch case/default not preceded by break or fallthrough comment
Hello Patrick Rudolph, Angel Pons, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35167
to look at the new patch set (#6).
Change subject: [WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U ......................................................................
[WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U
These changes are in accordance with the documentation:
[*] S-Platforms, Document Number: 332687-008EN [*] H-Platforms, Document Number: 332986-010EN [*] U/Y-Platforms, Document Number: 332990-008EN
Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/vr_config.c 1 file changed, 81 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35167/6
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: [WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35167/6/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/6/src/soc/intel/skylake/vr_co... PS6, Line 191: else if (tdp >= 25) { else should follow close brace '}'
https://review.coreboot.org/c/coreboot/+/35167/6/src/soc/intel/skylake/vr_co... PS6, Line 216: case PCI_DEVICE_ID_INTEL_SKL_ID_H_2: /* fallthrough */ Possible switch case/default not preceded by break or fallthrough comment
https://review.coreboot.org/c/coreboot/+/35167/6/src/soc/intel/skylake/vr_co... PS6, Line 217: case PCI_DEVICE_ID_INTEL_SKL_ID_H_EM: /* fallthrough */ Possible switch case/default not preceded by break or fallthrough comment
Hello Patrick Rudolph, Angel Pons, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35167
to look at the new patch set (#7).
Change subject: [WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U ......................................................................
[WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U
These changes are in accordance with the documentation:
[*] S-Platforms, Document Number: 332687-008EN [*] H-Platforms, Document Number: 332986-010EN [*] U/Y-Platforms, Document Number: 332990-008EN
Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/vr_config.c 1 file changed, 81 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35167/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: [WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35167/7/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/7/src/soc/intel/skylake/vr_co... PS7, Line 216: case PCI_DEVICE_ID_INTEL_SKL_ID_H_2: /* fallthrough */ Possible switch case/default not preceded by break or fallthrough comment
https://review.coreboot.org/c/coreboot/+/35167/7/src/soc/intel/skylake/vr_co... PS7, Line 217: case PCI_DEVICE_ID_INTEL_SKL_ID_H_EM: /* fallthrough */ Possible switch case/default not preceded by break or fallthrough comment
Hello Patrick Rudolph, Angel Pons, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35167
to look at the new patch set (#8).
Change subject: [WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U ......................................................................
[WIP] soc/skl/vr_config: Add VR config for SKL-S/H/U
These changes are in accordance with the documentation:
[*] S-Platforms, Document Number: 332687-008EN [*] H-Platforms, Document Number: 332986-010EN [*] U/Y-Platforms, Document Number: 332990-008EN
Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/vr_config.c 1 file changed, 82 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35167/8
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skl/vr_config: Add VR config for SKL-S/H/U/Y ......................................................................
Patch Set 19:
(1 comment)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/35167/2/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/2/src/soc/intel/skylake/vr_co... PS2, Line 176: else if (tdp >= 45) : icc_max[VR_IA_CORE] = VR_CFG_AMP(70);
SKL-H values appear on a different document: #332986 […]
Thanks for the help Done
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skl/vr_config: Add VR config for SKL-S/H/U/Y ......................................................................
Patch Set 19:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35167/3/src/soc/intel/skylake/vr_co... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/3/src/soc/intel/skylake/vr_co... PS3, Line 148: uint16_t icc_max[NUM_VR_DOMAINS] = { : VR_CFG_AMP(11.1), : VR_CFG_AMP(40), : VR_CFG_AMP(48), : VR_CFG_AMP(48), : };
Hmm, excuse me, but where are the Iccmax for the VR_RING domain? I see in the device tree for some b […]
The macro VR_CFG_ALL_DOMAINS_ICC takes this into account
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skl/vr_config: Add VR config for SKL-S/H/U/Y ......................................................................
Patch Set 20:
This change is ready for review.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skl/vr_config: Add VR config for SKL-S/H/U/Y ......................................................................
Patch Set 21: Code-Review+2
(1 comment)
Other than a typo, looks good to me. The code flow is much easier to follow now. Thanks!
https://review.coreboot.org/c/coreboot/+/35167/21/src/soc/intel/skylake/vr_c... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/21/src/soc/intel/skylake/vr_c... PS21, Line 268: Loadlane Loadline
Hello Aaron Durbin, Patrick Rudolph, Felix Held, Angel Pons, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35167
to look at the new patch set (#22).
Change subject: soc/skl/vr_config: Add VR config for SKL-S/H/U/Y ......................................................................
soc/skl/vr_config: Add VR config for SKL-S/H/U/Y
Icc/Loadline automatic detection is supported only for FSP2.0
These changes are in accordance with the documentation: [*] S-Platforms, Document Number: 332687-008EN [*] H-Platforms, Document Number: 332986-010EN [*] U/Y-Platforms, Document Number: 332990-008EN
Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/vr_config.c 2 files changed, 151 insertions(+), 106 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35167/22
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skl/vr_config: Add VR config for SKL-S/H/U/Y ......................................................................
Patch Set 22:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35167/21/src/soc/intel/skylake/vr_c... File src/soc/intel/skylake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/35167/21/src/soc/intel/skylake/vr_c... PS21, Line 268: Loadlane
Loadline
Done
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skl/vr_config: Add VR config for SKL-S/H/U/Y ......................................................................
Patch Set 22:
Inherit +2 from patchset 21. Difference is trivial
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skl/vr_config: Add VR config for SKL-S/H/U/Y ......................................................................
Patch Set 22: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35167 )
Change subject: soc/skl/vr_config: Add VR config for SKL-S/H/U/Y ......................................................................
soc/skl/vr_config: Add VR config for SKL-S/H/U/Y
Icc/Loadline automatic detection is supported only for FSP2.0
These changes are in accordance with the documentation: [*] S-Platforms, Document Number: 332687-008EN [*] H-Platforms, Document Number: 332986-010EN [*] U/Y-Platforms, Document Number: 332990-008EN
Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35167 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/vr_config.c 2 files changed, 151 insertions(+), 106 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index aebbbdf..de5428a 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -83,6 +83,16 @@ VR_GT_SLICED, NUM_VR_DOMAINS }; + +#define VR_CFG_ALL_DOMAINS_ICC(sa, ia, gt_unsl, gt_sl) \ + { \ + [VR_SYSTEM_AGENT] = VR_CFG_AMP(sa), \ + [VR_IA_CORE] = VR_CFG_AMP(ia), \ + [VR_RING] = VR_CFG_AMP(0), \ + [VR_GT_UNSLICED] = VR_CFG_AMP(gt_unsl), \ + [VR_GT_SLICED] = VR_CFG_AMP(gt_sl), \ + } + #else /* VrConfig Settings for 4 domains * 0 = System Agent, 1 = IA Core, @@ -95,8 +105,26 @@ VR_GT_SLICED, NUM_VR_DOMAINS }; + +#define VR_CFG_ALL_DOMAINS_ICC(sa, ia, gt_unsl, gt_sl) \ + { \ + [VR_SYSTEM_AGENT] = VR_CFG_AMP(sa), \ + [VR_IA_CORE] = VR_CFG_AMP(ia), \ + [VR_GT_UNSLICED] = VR_CFG_AMP(gt_unsl), \ + [VR_GT_SLICED] = VR_CFG_AMP(gt_sl), \ + } + #endif
+#define VR_CFG_ALL_DOMAINS_LOADLINE(sa, ia, gt_unsl, gt_sl) \ + { \ + [VR_SYSTEM_AGENT] = VR_CFG_MOHMS(sa), \ + [VR_IA_CORE] = VR_CFG_MOHMS(ia), \ + [VR_GT_UNSLICED] = VR_CFG_MOHMS(gt_unsl), \ + [VR_GT_SLICED] = VR_CFG_MOHMS(gt_sl), \ + } + + void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); #endif diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 121a344..fc23640 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -92,113 +92,139 @@ { const uint16_t tdp = cpu_get_power_max();
- static uint16_t mch_id = 0, igd_id = 0, lpc_id = 0; + static uint16_t mch_id = 0, igd_id = 0; if (!mch_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - mch_id = pci_read_config16(dev, PCI_DEVICE_ID); + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; } if (!igd_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (dev) - igd_id = pci_read_config16(dev, PCI_DEVICE_ID); - else - igd_id = 0xffff; - } - if (!lpc_id) { - struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - lpc_id = pci_read_config16(dev, PCI_DEVICE_ID); + igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; }
/* * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the * Iccmax is the same among KBL-Y but KBL-U/R. * Addendum for AML-Y #594883, IccMax for IA core is 28A. - * KBL-S #335195, KBL-H #335190 - * +----------------+-------------+---------------+------+-----+ - * | Domain/Setting | SA | IA | GTUS | GTS | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-S) | 11.1A | 100A | 48A | 48A | - * | | | ... | 45A | 45A | - * | | | 40A | 35A | 35A | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-H) | 11.1A (45W) | 68A | 55A | 55A | - * | | 6.6A (18W) | 60A | | | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | - * | | 4.5A(Others)| 29A(P/C) | | | - * | | | 32A(i3/i5) | | | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ + * KBL-S #335195, KBL-H #335190, SKL-S #332687, SKL-H #332986, + * SKL-U/Y #332990 + * + * Platform Segment SA IA GT (GT/GTx) + * --------------------------------------------------------------------- + * KBL/SKL-S (95W) quad 11.1 100 45 + * SKL-S (80W) quad 11.1 82 45 + * KBL/SKL-S (65W) quad 11.1 79 45 + * SKL-S (45W) quad 11.1 70 0 + * KBL/SKL-S (35W) quad 11.1 66 35 + * SKL-S (25W) quad 11.1 55 35 + * + * KBL/SKL-S (54W) dual 11.1 58 48 + * KBL/SKL-S (51W) dual 11.1 45 48 + * KBL/SKL-S (35W) dual 11.1 40 48 + * + * SKL-H + OPC (65W) GT4 quad 8 74 105/24 + * SKL-H + OPC (45W) GT4 quad 8 74 94/20 + * SKL-H + OPC (35W) GT4 quad 8 66 94/20 + * + * SKL-H (35W) GT2 dual 11.1 60 55 + * + * KBL/SKL-H (45W) GT2 quad 11.1 68 55 + * KBL-H (18W) GT2 quad 6.6 60 55 + * + * SKL-U + OPC (28W) GT3 dual 5.1 32 57/19 + * SKL-U + OPC (15W) GT3 dual 5.1 29 57/19 + * SKL-U (15W) GT2 dual 4.5 29 31 + * + * KBL-U/R + OPC (28W) GT3 dual 5.1 32 57/19 + * KBL-U/R + OPC (15W) GT3 dual 5.1 32 57/19 + * + * KBL-U/R (15W) GT2 quad 6 64 31 + * KBL-U/R (15W) GT1/2 dual 4.5 32 31 + * KBL-U/R (15W) GT2 quad 4.5 29 31 + * + * SKL/KBL-Y (6W) 4.1 24 24 + * SKL/KBL-Y (4.5W) 4.1 24 24 */
switch (mch_id) { + case PCI_DEVICE_ID_INTEL_SKL_ID_S_2: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_S: { - uint16_t icc_max[NUM_VR_DOMAINS] = { - VR_CFG_AMP(11.1), - VR_CFG_AMP(40), - VR_CFG_AMP(48), - VR_CFG_AMP(48), - }; + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 48, 48); if (tdp >= 54) icc_max[VR_IA_CORE] = VR_CFG_AMP(58); else if (tdp >= 51) icc_max[VR_IA_CORE] = VR_CFG_AMP(45);
return icc_max[domain]; - } + case PCI_DEVICE_ID_INTEL_SKL_ID_S_4: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_DT: { - uint16_t icc_max[NUM_VR_DOMAINS] = { - VR_CFG_AMP(11.1), - VR_CFG_AMP(66), - VR_CFG_AMP(45), - VR_CFG_AMP(45), - }; + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 55, 45, 45); if (tdp >= 91) icc_max[VR_IA_CORE] = VR_CFG_AMP(100); + else if (tdp >= 80) + icc_max[VR_IA_CORE] = VR_CFG_AMP(82); else if (tdp >= 65) icc_max[VR_IA_CORE] = VR_CFG_AMP(79); - else if (tdp >= 35) { - icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(35); + else if (tdp >= 45) { + icc_max[VR_IA_CORE] = VR_CFG_AMP(70); + icc_max[VR_GT_SLICED] = 0; + icc_max[VR_GT_UNSLICED] = 0; + } else if (tdp >= 25) { + if (tdp >= 35) + icc_max[VR_IA_CORE] = VR_CFG_AMP(66); + icc_max[VR_GT_SLICED] = VR_CFG_AMP(35); + icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(35); }
return icc_max[domain]; } - case PCI_DEVICE_ID_INTEL_KBL_ID_H: { - uint16_t icc_max[NUM_VR_DOMAINS] = { - VR_CFG_AMP(6.6), - VR_CFG_AMP(60), - VR_CFG_AMP(55), - VR_CFG_AMP(55), - }; + case PCI_DEVICE_ID_INTEL_SKL_ID_H_4: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 60, 94, 20); if (tdp >= 45) { + icc_max[VR_IA_CORE] = VR_CFG_AMP(74); + if (tdp >= 65) { + icc_max[VR_GT_SLICED] = VR_CFG_AMP(105); + icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(24); + } + } + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_SKL_ID_H_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_H_EM: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_H: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6.6, 60, 55, 55); + if (tdp >= 35) { + if (tdp >= 45) + icc_max[VR_IA_CORE] = VR_CFG_AMP(68); + icc_max[VR_SYSTEM_AGENT] = VR_CFG_AMP(11.1); - icc_max[VR_IA_CORE] = VR_CFG_AMP(68); }
return icc_max[domain]; } + case PCI_DEVICE_ID_INTEL_SKL_ID_U: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(5.1, 29, 57, 19); + if (tdp >= 28) + icc_max[VR_IA_CORE] = VR_CFG_AMP(32); + else if (igd_id != PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_1) { + const uint16_t icc_max_gt2[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_ICC(4.5, 29, 31, 31); + + return icc_max_gt2[domain]; + } + return icc_max[domain]; + } case PCI_DEVICE_ID_INTEL_KBL_U_R: { - static const uint16_t icc_max[NUM_VR_DOMAINS] = { - VR_CFG_AMP(6), - VR_CFG_AMP(64), - VR_CFG_AMP(31), - VR_CFG_AMP(31), - }; + const uint16_t icc_max[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_ICC(6, 64, 31, 31); return icc_max[domain]; } + case PCI_DEVICE_ID_INTEL_SKL_ID_Y: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_Y: { - uint16_t icc_max[NUM_VR_DOMAINS] = { - VR_CFG_AMP(4.1), - VR_CFG_AMP(24), - VR_CFG_AMP(24), - VR_CFG_AMP(24), - }; + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.1, 24, 24, 24);
if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) icc_max[VR_IA_CORE] = VR_CFG_AMP(28); @@ -206,12 +232,7 @@ return icc_max[domain]; } case PCI_DEVICE_ID_INTEL_KBL_ID_U: { - uint16_t icc_max[NUM_VR_DOMAINS] = { - VR_CFG_AMP(4.5), - VR_CFG_AMP(32), - VR_CFG_AMP(31), - VR_CFG_AMP(31), - }; + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.5, 32, 31, 31);
if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) @@ -220,7 +241,7 @@ return icc_max[domain]; } default: - printk(BIOS_ERR, "ERROR: Unknown MCH in VR-config\n"); + printk(BIOS_ERR, "ERROR: Unknown MCH (%u) in VR-config\n", mch_id); } return 0; } @@ -231,62 +252,58 @@ static uint16_t mch_id = 0, igd_id = 0; if (!mch_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - mch_id = pci_read_config16(dev, PCI_DEVICE_ID); + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; } if (!igd_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (dev) - igd_id = pci_read_config16(dev, PCI_DEVICE_ID); - else - igd_id = 0xffff; + igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; }
switch (mch_id) { - case PCI_DEVICE_ID_INTEL_KBL_ID_S: /* fallthrough */ - case PCI_DEVICE_ID_INTEL_KBL_ID_DT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_S_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_S_4: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_S: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_DT: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: { - static const uint16_t loadline[NUM_VR_DOMAINS] = { - VR_CFG_MOHMS(0), /* Not specified */ - VR_CFG_MOHMS(2.1), - VR_CFG_MOHMS(3.1), - VR_CFG_MOHMS(3.1), - }; - + /* SA Loadline is not specified */ + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(0, 2.1, 3.1, 3.1); return loadline[domain]; } + case PCI_DEVICE_ID_INTEL_SKL_ID_H_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_H_EM: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_H_4: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_H: { - static const uint16_t loadline[NUM_VR_DOMAINS] = { - VR_CFG_MOHMS(10), - VR_CFG_MOHMS(1.8), - VR_CFG_MOHMS(2.65), - VR_CFG_MOHMS(2.65), - }; + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10, 1.8, 2.65, 2.65); + + if (igd_id == PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM) { + const uint16_t loadline_gt4[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(6, 1.6, 1.4, 6); + return loadline_gt4[domain]; + }
return loadline[domain]; } + case PCI_DEVICE_ID_INTEL_SKL_ID_Y: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_Y: { - uint16_t loadline[NUM_VR_DOMAINS] = { - VR_CFG_MOHMS(18), - VR_CFG_MOHMS(5.9), - VR_CFG_MOHMS(5.7), - VR_CFG_MOHMS(5.7), - }; + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(18, 5.9, 5.7, 5.7);
if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) loadline[VR_IA_CORE] = VR_CFG_MOHMS(4);
return loadline[domain]; } - case PCI_DEVICE_ID_INTEL_KBL_U_R: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_U: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_U_R: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_U: { - uint16_t loadline[NUM_VR_DOMAINS] = { - VR_CFG_MOHMS(10.3), - VR_CFG_MOHMS(2.4), - VR_CFG_MOHMS(3.1), - VR_CFG_MOHMS(3.1), - }; + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1);
- if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || + if ((igd_id == PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_1) || + (igd_id == PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_2) || + (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) { loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2); loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6); @@ -295,7 +312,7 @@ return loadline[domain]; } default: - printk(BIOS_ERR, "ERROR: Unknown MCH in VR-config\n"); + printk(BIOS_ERR, "ERROR: Unknown MCH (%u) in VR-config\n", mch_id); } return 0; }
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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Maxim Polyakov (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)