Change in coreboot[master]: soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode - coreboot-gerrit

19 Feb 2021


      Attention is currently required from: Nico Huber, Tim Wawrzynczak, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50750 )
Change subject: soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode
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Patch Set 2:
(1 comment)
Patchset:
PS2:
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Looks like we have some macro naming alignment to work on across the SoC definitions to avoid the cu […]
Xeon-SP is an easy fix. APL/GLK doesn't seem to have the bit, but I'll add the macro anyway for consistency.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa
Gerrit-Change-Number: 50750
Gerrit-PatchSet: 2
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