Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 )

Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp/... 
File src/mainboard/intel/tglrvp/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp/... 
PS4, Line 91: if (spd_index > 0 && spd_index != 2) {
            : 
            : 		mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
            : 		spd_ptr = mainboard_get_spd_data();
            : 
            : 		mem_cfg->MemorySpdPtr00 = spd_ptr;
            : 		mem_cfg->MemorySpdPtr02 = spd_ptr;
            : 		mem_cfg->MemorySpdPtr04 = spd_ptr;
            : 		mem_cfg->MemorySpdPtr06 = spd_ptr;
            : 		mem_cfg->MemorySpdPtr08 = spd_ptr;
            : 		mem_cfg->MemorySpdPtr10 = spd_ptr;
            : 		mem_cfg->MemorySpdPtr12 = spd_ptr;
            : 		mem_cfg->MemorySpdPtr14 = spd_ptr;
            : 
            : 		mem_cfg->SpdAddressTable[0] = 0x0;
            : 		mem_cfg->SpdAddressTable[1] = 0x0;
            : 		mem_cfg->SpdAddressTable[2] = 0x0;
            : 		mem_cfg->SpdAddressTable[3] = 0x0;
            : 
            : 	} else {
            : 		mem_cfg->MemorySpdPtr00 = 0;
            : 		mem_cfg->MemorySpdPtr01 = 0;
            : 		mem_cfg->MemorySpdPtr10 = 0;
            : 		mem_cfg->MemorySpdPtr11 = 0;
            : 
            : 		mem_cfg->SpdAddressTable[0] = 0xA0;
            : 		mem_cfg->SpdAddressTable[1] = 0xA2;
            : 		mem_cfg->SpdAddressTable[2] = 0xA4;
            : 		mem_cfg->SpdAddressTable[3] = 0xA6;
            : 
            : 		mem_cfg->RcompResistor = mem_params.rcomp_resistor;
            : 		memcpy(&mem_cfg->RcompTarget, mem_params.rcomp_target, mem_params.rcomp_target_size);
            : 	}
            : 
            : 	memcpy(&mem_cfg->DqMapCpu2DramCh0, mem_params.dq_map, mem_params.dq_map_size);
            : 	memcpy(&mem_cfg->DqsMapCpu2DramCh0, mem_params.dqs_map, mem_params.dqs_map_size);
            : 
            : 	mem_cfg->DqPinsInterleaved = 0;
            : 	mem_cfg->MrcSafeConfig = 0x1;
            : 
            : 	/* Early Command Training */
            : 	mem_cfg->ECT = 1;
Any reason why this cannot use meminit_lpddr4x_dimm0() as provided by SoC code: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/m...

You might have to extent it if you want to support reading SPD from DIMM: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/i..., but I think that should still save a lot of code/logic duplication here.