Change in coreboot[master]: soc/intel/broadwell: Use `mmconf_resource()`

[Angel Pons (Code Review)]

Attention is currently required from: Nico Huber, Arthur Heymans, Patrick Rudolph.
Hello Nico Huber, Arthur Heymans, Patrick Rudolph,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/55488

to review the following change.

Change subject: soc/intel/broadwell: Use `mmconf_resource()`
......................................................................

soc/intel/broadwell: Use `mmconf_resource()`

Done for consistency with Haswell northbridge code.

Change-Id: Ibf665e3976934dafc6f3d98f16a20c026a499972
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/northbridge.c
1 file changed, 2 insertions(+), 35 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/55488/1

diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c
index 838b41b..b4f460f 100644
--- a/src/soc/intel/broadwell/northbridge.c
+++ b/src/soc/intel/broadwell/northbridge.c
@@ -35,40 +35,6 @@
    return pci_read_config32(sa_dev, BGSM) & ~1;
 }

-static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
-			u32 *len)
-{
-	u32 pciexbar_reg;
-
-	*base = 0;
-	*len = 0;
-
-	pciexbar_reg = pci_read_config32(dev, index);
-
-	if (!(pciexbar_reg & (1 << 0)))
-		return 0;
-
-	switch ((pciexbar_reg >> 1) & 3) {
-	case 0: // 256MB
-		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
-					(1 << 28));
-		*len = 256 * 1024 * 1024;
-		return 1;
-	case 1: // 128M
-		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
-					(1 << 28)|(1 << 27));
-		*len = 128 * 1024 * 1024;
-		return 1;
-	case 2: // 64M
-		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
-					(1 << 28)|(1 << 27)|(1 << 26));
-		*len = 64 * 1024 * 1024;
-		return 1;
-	}
-
-	return 0;
-}
-
 static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
 {
    u32 bar;
@@ -114,7 +80,6 @@
 };

struct fixed_mmio_descriptor mc_fixed_resources[] = {
-	{ PCIEXBAR, 0,               get_pcie_bar,      "PCIEXBAR" },
    { MCHBAR,   MCH_BASE_SIZE,   get_bar,           "MCHBAR"   },
    { DMIBAR,   DMI_BASE_SIZE,   get_bar,           "DMIBAR"   },
    { EPBAR,    EP_BASE_SIZE,    get_bar,           "EPBAR"    },
@@ -152,6 +117,8 @@
    	       __func__, mc_fixed_resources[i].description, index,
    	       (unsigned long)base, (unsigned long)(base + size - 1));
    }
+
+	mmconf_resource(dev, PCIEXBAR);
 }

/* Host Memory Map: