Change in coreboot[master]: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed

[Michał Żygowski (Code Review)]

Attention is currently required from: Michał Żygowski, Patrick Rudolph.
Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/59521

to look at the new patch set (#5).

Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
......................................................................

security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed

If TPM establishment is not asserted simply write to the MSR to unlock
memory on a TXT enabled platform. Previosuly on Sandybridge raminit the
algorithm was stuck at being unable to lock MPLL when the memory
controller was not unlocked with the MSR.

TEST=Successfully train the DRAM on Dell OptiPlex 9010 with i7-3770/Q77
with Intel TXT enabled

Signed-off-by: Michał Żygowski 
Change-Id: Idd29d163a2310f0b574fc72d575f23088ab1d11d
---
M src/security/intel/txt/romstage.c
M src/security/intel/txt/txt_register.h
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/59521/5