Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38058 )
Change subject: mb/gigabyte/ga-g41m-es2l/devicetree.cb: Indent with tabs ......................................................................
mb/gigabyte/ga-g41m-es2l/devicetree.cb: Indent with tabs
As on most other boards, use tabs to indent the devicetree.
Change-Id: If95f1ce6a5347658ecc32097a85b1b6bcc6a1114 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb 1 file changed, 148 insertions(+), 148 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/38058/1
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 13da3e8..76dd819 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -15,157 +15,157 @@ #
chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end - end - device domain 0 on # PCI domain - subsystemid 0x1458 0x5000 inherit - device pci 0.0 on # Host Bridge - subsystemid 0x1458 0x5000 - end - device pci 2.0 on # Integrated graphics controller - subsystemid 0x1458 0xd000 - end - device pci 2.1 on # Integrated graphics controller 2 - subsystemid 0x1458 0xd001 - end - device pci 3.0 off end # ME - device pci 3.1 off end # ME - chip southbridge/intel/i82801gx # Southbridge - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ports_implemented" = "0x3" - register "gpe0_en" = "0x40" + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + subsystemid 0x1458 0x5000 inherit + device pci 0.0 on # Host Bridge + subsystemid 0x1458 0x5000 + end + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1458 0xd000 + end + device pci 2.1 on # Integrated graphics controller 2 + subsystemid 0x1458 0xd001 + end + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x40"
- register "gen2_dec" = "0x007c0291" # HWM + register "gen2_dec" = "0x007c0291" # HWM
- device pci 1b.0 on # Audio - subsystemid 0x1458 0xa002 - end - device pci 1c.0 on end # PCIe 1 - device pci 1c.1 on # PCIe 2 (NIC) - device pci 00.0 on # PCI 10ec:8168 - subsystemid 0x1458 0xe000 - end - end - device pci 1c.2 off end # PCIe 3 - device pci 1c.3 off end # PCIe 4 - device pci 1d.0 on # USB - subsystemid 0x1458 0x5004 - end - device pci 1d.1 on # USB - subsystemid 0x1458 0x5004 - end - device pci 1d.2 on # USB - subsystemid 0x1458 0x5004 - end - device pci 1d.3 on # USB - subsystemid 0x1458 0x5004 - end - device pci 1d.7 on # USB - subsystemid 0x1458 0x5006 - end - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio - device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # ISA bridge - subsystemid 0x1458 0x5001 - chip superio/ite/it8718f # Super I/O - register "TMPIN1.mode" = "THERMAL_RESISTOR" - register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" - register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" + device pci 1b.0 on # Audio + subsystemid 0x1458 0xa002 + end + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2 (NIC) + device pci 00.0 on # PCI 10ec:8168 + subsystemid 0x1458 0xe000 + end + end + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1d.0 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.1 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.2 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.3 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.7 on # USB + subsystemid 0x1458 0x5006 + end + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # ISA bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8718f # Super I/O + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_DIODE" + register "TMPIN3.offset" = "0" + register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0"
- register "FAN1.mode" = "FAN_SMART_AUTOMATIC" - register "FAN1.smart.tmpin" = "3" - register "FAN1.smart.tmp_off" = "25" - register "FAN1.smart.tmp_start" = "30" - register "FAN1.smart.tmp_full" = "65" - register "FAN1.smart.tmp_delta" = "3" - register "FAN1.smart.smoothing" = "1" - register "FAN1.smart.pwm_start" = "0" - register "FAN1.smart.slope" = "10" + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "25" + register "FAN1.smart.tmp_start" = "30" + register "FAN1.smart.tmp_full" = "65" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "0" + register "FAN1.smart.slope" = "10"
- register "FAN2.mode" = "FAN_SMART_AUTOMATIC" - register "FAN2.smart.tmpin" = "3" - register "FAN2.smart.tmp_off" = "25" - register "FAN2.smart.tmp_start" = "30" - register "FAN2.smart.tmp_full" = "65" - register "FAN2.smart.tmp_delta" = "3" - register "FAN2.smart.smoothing" = "1" - register "FAN2.smart.pwm_start" = "0" - register "FAN2.smart.slope" = "10" + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = "3" + register "FAN2.smart.tmp_off" = "25" + register "FAN2.smart.tmp_start" = "30" + register "FAN2.smart.tmp_full" = "65" + register "FAN2.smart.tmp_delta" = "3" + register "FAN2.smart.smoothing" = "1" + register "FAN2.smart.pwm_start" = "0" + register "FAN2.smart.slope" = "10"
- device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - irq 0xf0 = 0x00 - irq 0xf1 = 0x80 - end - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - io 0x62 = 0x000 - drq 0x74 = 4 - irq 0xf0 = 0x08 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - irq 0x70 = 0x00 - io 0x62 = 0x000 - irq 0xf0 = 0x80 - irq 0xf1 = 0x00 - irq 0xf2 = 0x0a - irq 0xf3 = 0x80 - irq 0xf4 = 0x00 - irq 0xf5 = 0x00 - irq 0xf6 = 0xff - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - irq 0x70 = 1 - io 0x62 = 0x64 - irq 0xf0 = 0x48 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - irq 0x71 = 2 - irq 0xf0 = 0 - end - end - end - device pci 1f.1 on # PATA/IDE - subsystemid 0x1458 0xb004 - end - device pci 1f.2 on # SATA - subsystemid 0x1458 0xb005 - end - device pci 1f.3 on # SMbus - subsystemid 0x1458 0x5001 - end - end - end + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + irq 0xf0 = 0x00 + irq 0xf1 = 0x80 + end + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + io 0x62 = 0x000 + drq 0x74 = 4 + irq 0xf0 = 0x08 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + irq 0x70 = 0x00 + io 0x62 = 0x000 + irq 0xf0 = 0x80 + irq 0xf1 = 0x00 + irq 0xf2 = 0x0a + irq 0xf3 = 0x80 + irq 0xf4 = 0x00 + irq 0xf5 = 0x00 + irq 0xf6 = 0xff + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 1 + io 0x62 = 0x64 + irq 0xf0 = 0x48 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + irq 0x71 = 2 + irq 0xf0 = 0 + end + end + end + device pci 1f.1 on # PATA/IDE + subsystemid 0x1458 0xb004 + end + device pci 1f.2 on # SATA + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on # SMbus + subsystemid 0x1458 0x5001 + end + end + end end
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38058 )
Change subject: mb/gigabyte/ga-g41m-es2l/devicetree.cb: Indent with tabs ......................................................................
Patch Set 1: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38058 )
Change subject: mb/gigabyte/ga-g41m-es2l/devicetree.cb: Indent with tabs ......................................................................
mb/gigabyte/ga-g41m-es2l/devicetree.cb: Indent with tabs
As on most other boards, use tabs to indent the devicetree.
Change-Id: If95f1ce6a5347658ecc32097a85b1b6bcc6a1114 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38058 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb 1 file changed, 148 insertions(+), 148 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 13da3e8..76dd819 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -15,157 +15,157 @@ #
chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end - end - device domain 0 on # PCI domain - subsystemid 0x1458 0x5000 inherit - device pci 0.0 on # Host Bridge - subsystemid 0x1458 0x5000 - end - device pci 2.0 on # Integrated graphics controller - subsystemid 0x1458 0xd000 - end - device pci 2.1 on # Integrated graphics controller 2 - subsystemid 0x1458 0xd001 - end - device pci 3.0 off end # ME - device pci 3.1 off end # ME - chip southbridge/intel/i82801gx # Southbridge - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ports_implemented" = "0x3" - register "gpe0_en" = "0x40" + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + subsystemid 0x1458 0x5000 inherit + device pci 0.0 on # Host Bridge + subsystemid 0x1458 0x5000 + end + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1458 0xd000 + end + device pci 2.1 on # Integrated graphics controller 2 + subsystemid 0x1458 0xd001 + end + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x40"
- register "gen2_dec" = "0x007c0291" # HWM + register "gen2_dec" = "0x007c0291" # HWM
- device pci 1b.0 on # Audio - subsystemid 0x1458 0xa002 - end - device pci 1c.0 on end # PCIe 1 - device pci 1c.1 on # PCIe 2 (NIC) - device pci 00.0 on # PCI 10ec:8168 - subsystemid 0x1458 0xe000 - end - end - device pci 1c.2 off end # PCIe 3 - device pci 1c.3 off end # PCIe 4 - device pci 1d.0 on # USB - subsystemid 0x1458 0x5004 - end - device pci 1d.1 on # USB - subsystemid 0x1458 0x5004 - end - device pci 1d.2 on # USB - subsystemid 0x1458 0x5004 - end - device pci 1d.3 on # USB - subsystemid 0x1458 0x5004 - end - device pci 1d.7 on # USB - subsystemid 0x1458 0x5006 - end - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio - device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # ISA bridge - subsystemid 0x1458 0x5001 - chip superio/ite/it8718f # Super I/O - register "TMPIN1.mode" = "THERMAL_RESISTOR" - register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" - register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" + device pci 1b.0 on # Audio + subsystemid 0x1458 0xa002 + end + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2 (NIC) + device pci 00.0 on # PCI 10ec:8168 + subsystemid 0x1458 0xe000 + end + end + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1d.0 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.1 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.2 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.3 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.7 on # USB + subsystemid 0x1458 0x5006 + end + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # ISA bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8718f # Super I/O + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_DIODE" + register "TMPIN3.offset" = "0" + register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0"
- register "FAN1.mode" = "FAN_SMART_AUTOMATIC" - register "FAN1.smart.tmpin" = "3" - register "FAN1.smart.tmp_off" = "25" - register "FAN1.smart.tmp_start" = "30" - register "FAN1.smart.tmp_full" = "65" - register "FAN1.smart.tmp_delta" = "3" - register "FAN1.smart.smoothing" = "1" - register "FAN1.smart.pwm_start" = "0" - register "FAN1.smart.slope" = "10" + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "25" + register "FAN1.smart.tmp_start" = "30" + register "FAN1.smart.tmp_full" = "65" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "0" + register "FAN1.smart.slope" = "10"
- register "FAN2.mode" = "FAN_SMART_AUTOMATIC" - register "FAN2.smart.tmpin" = "3" - register "FAN2.smart.tmp_off" = "25" - register "FAN2.smart.tmp_start" = "30" - register "FAN2.smart.tmp_full" = "65" - register "FAN2.smart.tmp_delta" = "3" - register "FAN2.smart.smoothing" = "1" - register "FAN2.smart.pwm_start" = "0" - register "FAN2.smart.slope" = "10" + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = "3" + register "FAN2.smart.tmp_off" = "25" + register "FAN2.smart.tmp_start" = "30" + register "FAN2.smart.tmp_full" = "65" + register "FAN2.smart.tmp_delta" = "3" + register "FAN2.smart.smoothing" = "1" + register "FAN2.smart.pwm_start" = "0" + register "FAN2.smart.slope" = "10"
- device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - irq 0xf0 = 0x00 - irq 0xf1 = 0x80 - end - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - io 0x62 = 0x000 - drq 0x74 = 4 - irq 0xf0 = 0x08 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - irq 0x70 = 0x00 - io 0x62 = 0x000 - irq 0xf0 = 0x80 - irq 0xf1 = 0x00 - irq 0xf2 = 0x0a - irq 0xf3 = 0x80 - irq 0xf4 = 0x00 - irq 0xf5 = 0x00 - irq 0xf6 = 0xff - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - irq 0x70 = 1 - io 0x62 = 0x64 - irq 0xf0 = 0x48 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - irq 0x71 = 2 - irq 0xf0 = 0 - end - end - end - device pci 1f.1 on # PATA/IDE - subsystemid 0x1458 0xb004 - end - device pci 1f.2 on # SATA - subsystemid 0x1458 0xb005 - end - device pci 1f.3 on # SMbus - subsystemid 0x1458 0x5001 - end - end - end + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + irq 0xf0 = 0x00 + irq 0xf1 = 0x80 + end + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + io 0x62 = 0x000 + drq 0x74 = 4 + irq 0xf0 = 0x08 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + irq 0x70 = 0x00 + io 0x62 = 0x000 + irq 0xf0 = 0x80 + irq 0xf1 = 0x00 + irq 0xf2 = 0x0a + irq 0xf3 = 0x80 + irq 0xf4 = 0x00 + irq 0xf5 = 0x00 + irq 0xf6 = 0xff + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 1 + io 0x62 = 0x64 + irq 0xf0 = 0x48 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + irq 0x71 = 2 + irq 0xf0 = 0 + end + end + end + device pci 1f.1 on # PATA/IDE + subsystemid 0x1458 0xb004 + end + device pci 1f.2 on # SATA + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on # SMbus + subsystemid 0x1458 0x5001 + end + end + end end
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Angel Pons (Code Review) -
Nico Huber (Code Review)