Change in coreboot[master]: mb/purism/librem_skl: drop SataSpeedLimit restriction
Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40909 ) Change subject: mb/purism/librem_skl: drop SataSpeedLimit restriction ...................................................................... mb/purism/librem_skl: drop SataSpeedLimit restriction SataSpeedLimit was set to 3Gbps to work around issues which are now known to be the result of incorrect FSP behavior. Since SataPwrOptEnable is now set at the SoC level and ensures the SIR registers are correctly programmed, we can re-enable 6Gbps operation works without errors. Test: build/boot Librem 13v2 with both m.2 and 2.5" SATA drives, check dmesg for errors. Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> --- M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/40909/1 diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index f69c482..89e3841 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -51,7 +51,6 @@ register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" - register "SataSpeedLimit" = "2" register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index f5b8b99..308688a 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -51,7 +51,6 @@ register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" - register "SataSpeedLimit" = "2" register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/40909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Gerrit-Change-Number: 40909 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> Gerrit-MessageType: newchange
Matt DeVillier has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/40909 ) Change subject: mb/purism/librem_skl: drop SataSpeedLimit restriction ...................................................................... mb/purism/librem_skl: drop SataSpeedLimit restriction SataSpeedLimit was set to 3Gbps to work around issues which are now known to be the result of incorrect FSP behavior. Since SataPwrOptEnable is now set at the SoC level and ensures the SIR registers are correctly programmed, we can re-enable 6Gbps operation without errors. Test: build/boot Librem 13v2 with both m.2 and 2.5" SATA drives, check dmesg for errors. Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> --- M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/40909/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Gerrit-Change-Number: 40909 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> Gerrit-MessageType: newpatchset
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40909 ) Change subject: mb/purism/librem_skl: drop SataSpeedLimit restriction ...................................................................... Patch Set 2: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/40909/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40909/2//COMMIT_MSG@10 PS2, Line 10: is start this on the next line? it's a tad bit too long Same for the following line -- To view, visit https://review.coreboot.org/c/coreboot/+/40909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Gerrit-Change-Number: 40909 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Thu, 30 Apr 2020 22:10:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Hello build bot (Jenkins), Angel Pons, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40909 to look at the new patch set (#3). Change subject: mb/purism/librem_skl: drop SataSpeedLimit restriction ...................................................................... mb/purism/librem_skl: drop SataSpeedLimit restriction SataSpeedLimit was set to 3Gbps to work around issues which are now known to be the result of incorrect FSP behavior. Since SataPwrOptEnable is now set at the SoC level and ensures the SIR registers are correctly programmed, we can re-enable 6Gbps operation without errors. Test: build/boot Librem 13v2 with both m.2 and 2.5" SATA drives, check dmesg for errors. Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> --- M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/40909/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/40909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Gerrit-Change-Number: 40909 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-MessageType: newpatchset
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40909 ) Change subject: mb/purism/librem_skl: drop SataSpeedLimit restriction ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/40909/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40909/2//COMMIT_MSG@10 PS2, Line 10: is
start this on the next line? it's a tad bit too long […] Done
-- To view, visit https://review.coreboot.org/c/coreboot/+/40909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Gerrit-Change-Number: 40909 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Thu, 30 Apr 2020 22:12:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus@gmail.com> Gerrit-MessageType: comment
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40909 ) Change subject: mb/purism/librem_skl: drop SataSpeedLimit restriction ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/40909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Gerrit-Change-Number: 40909 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Fri, 01 May 2020 11:47:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40909 ) Change subject: mb/purism/librem_skl: drop SataSpeedLimit restriction ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Gerrit-Change-Number: 40909 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Fri, 01 May 2020 15:07:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40909 ) Change subject: mb/purism/librem_skl: drop SataSpeedLimit restriction ...................................................................... mb/purism/librem_skl: drop SataSpeedLimit restriction SataSpeedLimit was set to 3Gbps to work around issues which are now known to be the result of incorrect FSP behavior. Since SataPwrOptEnable is now set at the SoC level and ensures the SIR registers are correctly programmed, we can re-enable 6Gbps operation without errors. Test: build/boot Librem 13v2 with both m.2 and 2.5" SATA drives, check dmesg for errors. Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40909 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> --- M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb 2 files changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 6c55af6..b15dc2d 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -54,7 +54,6 @@ register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" - register "SataSpeedLimit" = "2" register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index f481352..d273462 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -54,7 +54,6 @@ register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" - register "SataSpeedLimit" = "2" register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/40909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Gerrit-Change-Number: 40909 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-MessageType: merged
participants (5)
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Angel Pons (Code Review) -
Matt DeVillier (Code Review)
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Michael Niewöhner (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)