Change in coreboot[master]: soc/intel/tigerlake: Remove Jasper Lake SoC references

[Aamir Bohra (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39774

to look at the new patch set (#7).

Change subject: soc/intel/tigerlake: Remove Jasper Lake SoC references
......................................................................

soc/intel/tigerlake: Remove Jasper Lake SoC references

This implementation removes all JSL references from the TGL SoC code.
It also removes scs.asl since it does not apply for Tiger Lake.

Additionally, mainboard code changes are done to support build.

BUG=b:150217037
TEST=build tglrvp and volteer

Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727
Signed-off-by: Aamir Bohra 
---
M src/mainboard/google/volteer/romstage.c
M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
M src/mainboard/intel/tglrvp/romstage_fsp_params.c
M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/acpi/pci_irqs.asl
D src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl
D src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl
D src/soc/intel/tigerlake/acpi/scs.asl
M src/soc/intel/tigerlake/acpi/xhci.asl
D src/soc/intel/tigerlake/acpi/xhci_jsl.asl
D src/soc/intel/tigerlake/acpi/xhci_tgl.asl
M src/soc/intel/tigerlake/bootblock/pch.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/espi.c
R src/soc/intel/tigerlake/fsp_params.c
D src/soc/intel/tigerlake/fsp_params_jsl.c
R src/soc/intel/tigerlake/gpio.c
D src/soc/intel/tigerlake/gpio_jsl.c
M src/soc/intel/tigerlake/include/soc/gpio.h
M src/soc/intel/tigerlake/include/soc/gpio_defs.h
D src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h
D src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h
M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
D src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
D src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h
M src/soc/intel/tigerlake/include/soc/iomap.h
M src/soc/intel/tigerlake/include/soc/irq.h
D src/soc/intel/tigerlake/include/soc/irq_jsl.h
D src/soc/intel/tigerlake/include/soc/irq_tgl.h
R src/soc/intel/tigerlake/include/soc/meminit.h
D src/soc/intel/tigerlake/include/soc/meminit_jsl.h
M src/soc/intel/tigerlake/include/soc/pch.h
M src/soc/intel/tigerlake/include/soc/pci_devs.h
M src/soc/intel/tigerlake/include/soc/pmc.h
R src/soc/intel/tigerlake/meminit.c
D src/soc/intel/tigerlake/meminit_jsl.c
M src/soc/intel/tigerlake/romstage/Makefile.inc
R src/soc/intel/tigerlake/romstage/fsp_params.c
D src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
41 files changed, 992 insertions(+), 3,041 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39774/7