Change in coreboot[master]: soc/amd/common: Add func to clear eSPI IO & memory decode ranges

[Raul Rangel (Code Review)]

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51748 )

Change subject: soc/amd/common: Add func to clear eSPI IO & memory decode ranges
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soc/amd/common: Add func to clear eSPI IO & memory decode ranges

Previously, the eSPI code would only add to existing decode ranges, and
there wasn't any way to clear ranges.  This clears all the ranges so
the eSPI configuration can start fresh.

BUG=b:183207262, b:183974365
TEST=Verify on Guybrush

Signed-off-by: Martin Roth 
Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
Reviewed-by: Furquan Shaikh 
---
M src/soc/amd/common/block/include/amdblocks/espi.h
M src/soc/amd/common/block/lpc/espi_util.c
2 files changed, 28 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Raul Rangel: Looks good to me, approved

diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h
index c593e02..7ca5b05 100644
--- a/src/soc/amd/common/block/include/amdblocks/espi.h
+++ b/src/soc/amd/common/block/include/amdblocks/espi.h
@@ -107,6 +107,13 @@
 void espi_configure_decodes(void);

/*
+ * Clear all configured eSPI memory and I/O decode ranges.  This is useful for changing
+ * the decodes, or if something else has previously setup decode windows that conflict
+ * with the windows that coreboot needs.
+ */
+void espi_clear_decodes(void);
+
+/*
  * In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading
  * SPIBASE. This is required for cases where verstage runs on PSP.
  */
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 0878fb7..152cdd9 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -98,6 +98,27 @@
    return -1;
 }

+void espi_clear_decodes(void)
+{
+	unsigned int idx;
+
+	/* First turn off all enable bits, then zero base, range, and size registers */
+	/*
+	 * There is currently a bug where the SMU will lock up at times if the port80h enable
+	 * bit is cleared.  See b/183974365
+	 */
+	espi_write16(ESPI_DECODE, (espi_read16(ESPI_DECODE) & ESPI_DECODE_IO_0x80_EN));
+
+	for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) {
+		espi_write16(ESPI_IO_RANGE_BASE(idx), 0);
+		espi_write8(ESPI_IO_RANGE_SIZE(idx), 0);
+	}
+	for (idx = 0; idx < ESPI_GENERIC_MMIO_WIN_COUNT; idx++) {
+		espi_write32(ESPI_MMIO_RANGE_BASE(idx), 0);
+		espi_write16(ESPI_MMIO_RANGE_SIZE(idx), 0);
+	}
+}
+
 /*
  * Returns decode enable bits for standard IO port addresses. If port address is not supported
  * by standard decode or if the size of window is not 1, then it returns -1.