Change in coreboot[master]: soc/intel/alderlake: Enable VT-d

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Meera Ravindranath, Ronak Kanabar, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51849 )

Change subject: soc/intel/alderlake: Enable VT-d
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Patch Set 5:

(1 comment)

File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/51849/comment/76673806_f3abf3d4 
PS5, Line 204: 		#if (GFXVT_BASE_ADDRESS == 0)
             : 			#error "Error: GFXVT_BASE_ADDRESS should be non-zero for enabling VT-d!"
             : 		#endif
> @Meera, you can add this check at stating of the file, no need to do inside exact code if you want

Sure, so if you check that the user wants VT-d enabled (by checking that `InternalGfx == 1`), and you still find the base address is 0, then just set VtdIgdEnable to 0 and print a warning, then there's no hang, can do the same for the other Vtd options.
These BARs are defined in soc/iomap.h, the odds of them getting redefined to 0 seems small to me?