[M] Change in coreboot[master]: drivers/intel/fsp2_0: Update MRC cache in ramstage

[Julius Werner (Code Review)]

Attention is currently required from: Kangheui Won, Reka Norman, Tim Wawrzynczak, Paul Menzel, Angel Pons, Arthur Heymans, Andrey Petrov.

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67669 )

Change subject: drivers/intel/fsp2_0: Update MRC cache in ramstage
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Patch Set 1:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/67669/comment/b9d0241a_b134e5c4 
PS1, Line 18:
> Yeah, I found that too and considered adding it there. But it looks very generic, so I wasn't sure if we wanted to add platform-specific stuff to it.

Oh, nevermind, I somehow thought that was still in the FSP code. Yeah we probably don't want to put it there.

Patchset:

PS1:
> Ok, sounds good. […]

Does anyone other than Chrome OS care about this? I would bet we're the only ones actually shipping ME_RW updates now. So if for us all the platforms that would be slower with the new flow all already branched, and we expect it to work fine on all future platforms, it should be okay.