[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Remove unnecessary op

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86911?usp=email )

Change subject: mb/starlabs/starbook/mtl: Remove unnecessary op
......................................................................

mb/starlabs/starbook/mtl: Remove unnecessary op

The default for DQS interleaving is 0, so don't set it to 0.

Change-Id: I5f828aa3a28947c2f88eaf36cc7bc8ad68812cb2
Signed-off-by: Sean Rhodes 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86911
Tested-by: build bot (Jenkins) 
Reviewed-by: Matt DeVillier 
---
M src/mainboard/starlabs/starbook/variants/mtl/romstage.c
1 file changed, 0 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Matt DeVillier: Looks good to me, approved

diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index 3e5291f..b593a8c 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -11,9 +11,6 @@
    	.type = MEM_TYPE_DDR5,
    	.ect = true,
    	.UserBd = BOARD_TYPE_ULT_ULX,
-		.ddr_config = {
-			.dq_pins_interleaved = false,
-		},
    	.rcomp = {
    		.resistor = 100,
    		.targets = {70, 30, 25, 25, 25},