Attention is currently required from: Hung-Te Lin, Yu-Ping Wu.
Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85930?usp=email )
Change subject: soc/mediatek/common/dp: Correct the settings in dptx_hal_set_msa ......................................................................
soc/mediatek/common/dp: Correct the settings in dptx_hal_set_msa
Correct the settings according to Linux kenrel driver. The related settings can be found in [1]:
[1]: https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/mediatek/mtk_d...
TEST=emerge-rauru coreboot; check FW screen on Ciri and Navi
Change-Id: I4ba7da74ce6394240513c482b19ec879b1a0a619 Signed-off-by: Yidi Lin yidilin@chromium.org --- M src/soc/mediatek/common/dp/dptx_hal_common.c 1 file changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/85930/1
diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c index 3ba95d1..89da19c 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_common.c +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -137,6 +137,7 @@ htotal = ha + hsync + hbp + hfp; vtotal = va + vsync + vbp + vfp;
+ /* horizontal */ DP_WRITE2BYTE(mtk_dp, REG_3010_DP_ENCODER0_P0, htotal); DP_WRITE2BYTE(mtk_dp, REG_3018_DP_ENCODER0_P0, hsync + hbp); mtk_dp_mask(mtk_dp, REG_3028_DP_ENCODER0_P0, @@ -146,7 +147,8 @@ 0 << HSP_SW_DP_ENCODER0_P0_FLDMASK_POS, HSP_SW_DP_ENCODER0_P0_FLDMASK); DP_WRITE2BYTE(mtk_dp, REG_3020_DP_ENCODER0_P0, ha); - DP_WRITE2BYTE(mtk_dp, REG_3014_DP_ENCODER0_P0, va); + /* vertical */ + DP_WRITE2BYTE(mtk_dp, REG_3014_DP_ENCODER0_P0, vtotal); DP_WRITE2BYTE(mtk_dp, REG_301C_DP_ENCODER0_P0, vsync + vbp); mtk_dp_mask(mtk_dp, REG_302C_DP_ENCODER0_P0, vsync << VSW_SW_DP_ENCODER0_P0_FLDMASK_POS, @@ -155,14 +157,16 @@ 0 << VSP_SW_DP_ENCODER0_P0_FLDMASK_POS, VSP_SW_DP_ENCODER0_P0_FLDMASK); DP_WRITE2BYTE(mtk_dp, REG_3024_DP_ENCODER0_P0, va); + /* horizontal */ DP_WRITE2BYTE(mtk_dp, REG_3064_DP_ENCODER0_P0, ha); DP_WRITE2BYTE(mtk_dp, REG_3154_DP_ENCODER0_P0, htotal); DP_WRITE2BYTE(mtk_dp, REG_3158_DP_ENCODER0_P0, hfp); - DP_WRITE2BYTE(mtk_dp, REG_315C_DP_ENCODER0_P0, vsync); + DP_WRITE2BYTE(mtk_dp, REG_315C_DP_ENCODER0_P0, hsync); DP_WRITE2BYTE(mtk_dp, REG_3160_DP_ENCODER0_P0, hsync + hbp); DP_WRITE2BYTE(mtk_dp, REG_3164_DP_ENCODER0_P0, ha); + /* vertical */ DP_WRITE2BYTE(mtk_dp, REG_3168_DP_ENCODER0_P0, vtotal); - DP_WRITE2BYTE(mtk_dp, REG_316C_DP_ENCODER0_P0, hfp); + DP_WRITE2BYTE(mtk_dp, REG_316C_DP_ENCODER0_P0, vfp); DP_WRITE2BYTE(mtk_dp, REG_3170_DP_ENCODER0_P0, vsync); DP_WRITE2BYTE(mtk_dp, REG_3174_DP_ENCODER0_P0, vsync + vbp); DP_WRITE2BYTE(mtk_dp, REG_3178_DP_ENCODER0_P0, va);