Change in coreboot[master]: soc/amd/common/include/spi: add Cezanne-specific comment

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60117 )

Change subject: soc/amd/common/include/spi: add Cezanne-specific comment
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soc/amd/common/include/spi: add Cezanne-specific comment

The Cezanne PPR #56569 Rev 3.03 has one more SPI FIFO bytes defined
compared to the previous generations. It is unclear if adding some
special handling for Cezanne would be worth the effort, since the
current code just doesn't use the last byte which should be safe to do,
since this only affects the maximum number of bytes that can be used for
one SPI transaction. Having another byte to use on Cezanne wouldn't
reduce the number of SPI transactions to write a 256 byte data block.

Signed-off-by: Felix Held 
Change-Id: Ic730f4fe838f59066120c811833995c132c84c1c
---
M src/soc/amd/common/block/include/amdblocks/spi.h
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/60117/1

diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h
index 4efed68..4be3739 100644
--- a/src/soc/amd/common/block/include/amdblocks/spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/spi.h
@@ -71,7 +71,7 @@
 #define   SPI_RD4DW_EN_HOST		BIT(15)

#define SPI_FIFO			0x80
-#define SPI_FIFO_LAST_BYTE		0xc6
+#define SPI_FIFO_LAST_BYTE		0xc6 /* 0xc7 for Cezanne */
 #define SPI_FIFO_DEPTH			(SPI_FIFO_LAST_BYTE - SPI_FIFO + 1)

struct spi_config {