Timothy Pearson (tpearson@raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14191
-gerrit
commit c37f56a5033eff98e84ea5a5eab8260dd0ac876b Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Wed Mar 30 13:07:47 2016 -0500
nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs
During power on from cold (S5) state, numerous MCEs are generated before DRAM training starts, e.g. during HT link training. Clear these MCEs before DRAM training start, and report any MCEs generated during DRAM training.
Change-Id: I7d047571242e5bd041e4aac22c1ec1d7d26ef0e6 Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 34 ++++++++++++++++++-------- 2 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 6292f0b..2de7521 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8048,6 +8048,10 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006, dword); }
+ /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + printk(BIOS_DEBUG, "%s: Done\n", __func__); }
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 2ebd093..07eb0bd 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -250,16 +250,30 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) pDCTstat = pDCTstatA + Node;
if (NodePresent_D(Node)) { - /* Clear MC4 error status */ - pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); - pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - if (pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + dev = pDCTstat->dev_map; + reg = 0x40 + (Node << 3); /* Dram Base Node 0 + index */ + val = Get_NB32(dev, reg); + + /* WE/RE is checked */ + if ((val & 0x3) == 0x3) { /* Node has dram populated */ + uint32_t mc4_status_high = pci_read_config32(pDCTstat->dev_nbmisc, 0x4c); + uint32_t mc4_status_low = pci_read_config32(pDCTstat->dev_nbmisc, 0x48); + if (mc4_status_high != 0) { + printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected!\n" + "Signature: %08x%08x\n", mc4_status_high, mc4_status_low); + } + + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + + /* Restore previous MCA error handling settings */ + if (pDCTstat->mca_config_backed_up) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; + dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + } } } }
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Timothy Pearson