Change in coreboot[master]: nb/amd/mct: Fix building with DQS_TRAIN_DEBUG > 0

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20975

Change subject: nb/amd/mct: Fix building with DQS_TRAIN_DEBUG > 0
......................................................................

nb/amd/mct: Fix building with DQS_TRAIN_DEBUG > 0

Change-Id: I7d56f4cb5660466b7cf193a08adbfc17834c7a50
Signed-off-by: Arthur Heymans 
---
M src/northbridge/amd/amdmct/mct/mctdqs_d.c
M src/northbridge/amd/amdmct/mct/mctsrc.c
M src/northbridge/amd/amdmct/mct/mcttmrl.c
3 files changed, 4 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/20975/1

diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 174c481..0c2bc2d 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -16,6 +16,7 @@
 #include <northbridge/amd/amdfam10/debug.h>
 #include <cpu/x86/cr.h>
 #include <cpu/amd/mtrr.h>
+#include <console/console.h>

#include "mct_d.h"
 #include "mct_d_gcc.h"
@@ -341,7 +342,7 @@
    {
    	u8 val;
    	u8 i;
-		u8 Channel, Receiver, Dir;
+		u8 Receiver, Dir;
    	u8 *p;

for (Dir = 0; Dir < 2; Dir++) {
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c
index 3a78620..eee7901 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -16,6 +16,7 @@

#include <northbridge/amd/amdfam10/debug.h>
 #include <cpu/x86/cr.h>
+#include <console/console.h>

#include "mct_d.h"
 #include "mct_d_gcc.h"
@@ -460,7 +461,6 @@

#if DQS_TRAIN_DEBUG > 0
    {
-		u8 Channel;
    	printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n");
    	for (Channel = 0; Channel < 2; Channel++) {
    		printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]);
@@ -470,8 +470,6 @@

#if DQS_TRAIN_DEBUG > 0
    {
-		u8 val;
-		u8 Channel, Receiver;
    	u8 i;
    	u8 *p;

diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c
index 81ec5f9..67093d9 100644
--- a/src/northbridge/amd/amdmct/mct/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */

+#include <console/console.h>
 #include <cpu/x86/cr.h>

#include "mct_d.h"
@@ -197,7 +198,6 @@

#if DQS_TRAIN_DEBUG > 0
    {
-		u8 Channel;
    	printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n");
    	for (Channel = 0; Channel < 2; Channel++) {
    		printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]);