Change in coreboot[master]: soc/intel/../thermal: Refactor PCH Thermal Configuration common API

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59209 )

Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
......................................................................

soc/intel/../thermal: Refactor PCH Thermal Configuration common API

Thermal configuration has evolved over PCH generations where
latest PCH has provided an option to allow thermal configuration
using PMC PWRMBASE registers.

This patch adds an option for impacted SoC to select the Kconfig
for allowing thermal configuration using PMC PCH MMIO space.

TODO: Combine all changes for now till we split it meaningfully.

Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0
Signed-off-by: Subrata Banik 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/common/block/thermal/Kconfig
M src/soc/intel/common/block/thermal/thermal.c
3 files changed, 36 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59209/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 58b9051..796f7bc 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -68,6 +68,8 @@
    select SOC_INTEL_COMMON_BLOCK_SMM
    select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
    select SOC_INTEL_COMMON_BLOCK_TCSS
+	select SOC_INTEL_COMMON_BLOCK_THERMAL
+	select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
    select SOC_INTEL_COMMON_BLOCK_USB4
    select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
    select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
diff --git a/src/soc/intel/common/block/thermal/Kconfig b/src/soc/intel/common/block/thermal/Kconfig
index 0605176..d723f25 100644
--- a/src/soc/intel/common/block/thermal/Kconfig
+++ b/src/soc/intel/common/block/thermal/Kconfig
@@ -3,3 +3,11 @@
    default n
    help
      This option allows to configure PCH thermal registers for supported PCH.
+
+config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
+	bool
+	depends on SOC_INTEL_COMMON_BLOCK_THERMAL
+	default n
+	help
+	  This option allows to configure PCH thermal registers using PMC PWRMBASE
+	  for chipsets since Tiger Lake PCH.
diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c
index f886995..b5b7be8 100644
--- a/src/soc/intel/common/block/thermal/thermal.c
+++ b/src/soc/intel/common/block/thermal/thermal.c
@@ -40,8 +40,8 @@
    return ltt_value;
 }

-/* Enable thermal sensor power management */
-void pch_thermal_configuration(void)
+/* Enable thermal sensor power management using PCI Thermal device */
+static void pch_pci_thermal_configuration(void)
 {
    uint16_t reg16;
    uintptr_t thermalbar;
@@ -74,3 +74,27 @@
    reg16 |= pch_get_ltt_value(dev);
    write16((uint16_t *)thermalbar_pm, reg16);
 }
+
+/* Enable thermal sensor power management using PMC PCH device */
+static void pch_pmc_thermal_configuration(void)
+{
+
+}
+
+/*
+ * Thermal configuration has evolved over time. With older platform the
+ * thermal device is sitting over PCI and allow to configure its configuration
+ * register by accessing the PCI configuration space or MMIO space.
+ *
+ * Since Tiger Lake, thermal registers are being moved behind the PMC PCI device
+ * hence, accessing thermal configuration registers would need making access
+ * to PWRMBASE. In this case SoC Kconfig to select
+ * SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to allow thermal configuration.
+ */
+void pch_thermal_configuration(void)
+{
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC))
+		return pch_pmc_thermal_configuration();
+
+	pch_pci_thermal_configuration();
+}