[S] Change in coreboot[master]: soc/intel/meteorlake: Add `.final` to check FSP reset pending request

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli, Kapil Porwal, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75310 )

Change subject: soc/intel/meteorlake: Add `.final` to check FSP reset pending request
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/75310/comment/cdc0156a_6a0d952a 
PS1, Line 13: As per recent debug it has been found that, FSP is accumulating all
            : platform resets and executing a single reset from FSP Notify Phase.
> > If FSP-M requests a reset, when would the reset be done? Ideally, it would happen as early as possible to minimise boot times.
>
> I know and that is also making me upset about the design. Raised a bug to start the discussion. We can't delay FSP-M reset to FSP notify and seems this is what happening on MTL.
> > Executing FSP-S and most of ramstage doesn't make much sense if we're going to reboot anyway.
>
> yeah

some additional debug information.

Deferring the FSP-M related reset to FSP notify is based on if MRC data is valid or not. In case MRC Data not valid, then only the reset request will move to FSP-notify which we need to handle now inside coreboot.

```
[SPEW ]  MRC Data not valid. Postpone reset to DXE
```