Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 14 files changed, 470 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46054/1
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig new file mode 100644 index 0000000..5183886 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -0,0 +1,84 @@ +if BOARD_INTEL_ADLRVP_P + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select DRIVERS_I2C_HID + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_USB_ACPI + select DRIVERS_SPI_ACPI + select GENERATE_SMBIOS_TABLES + select SOC_INTEL_ALDERLAKE + select MAINBOARD_USES_IFD_EC_REGION + select DRIVERS_UART_8250IO + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_MANUAL_RECOVERY + +config MAINBOARD_DIR + string + default "intel/adlrvp" + +config VARIANT_DIR + string + default "adlrvp_p" + +config GBB_HWID + string + depends on CHROMEOS + default "ADLRVPP" + +config MAINBOARD_PART_NUMBER + string + default "adlrvp" + +config MAINBOARD_FAMILY + string + default "Intel_adlrvp" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +choice ADL_EC + prompt "ON BOARD EC" + default ADL_INTEL_EC + help + This option allows you to select the on board EC to use. + Select whether the board has Intel EC or Chrome EC + +config ADL_CHROME_EC + bool "Chrome EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_ACPI + +config ADL_INTEL_EC + bool "Intel EC" + select EC_ACPI + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC +endchoice + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + +config UART_FOR_CONSOLE + int + default 0 +endif diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name new file mode 100644 index 0000000..4bf0d89 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_ADLRVP_P + bool "Alderlake-P RVP" diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc new file mode 100644 index 0000000..7422a7a --- /dev/null +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -0,0 +1,14 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +subdirs-y += ../common +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/adlrvp/board_info.txt b/src/mainboard/intel/adlrvp/board_info.txt new file mode 100644 index 0000000..be99df8 --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Alderlake rvp +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/adlrvp/bootblock.c b/src/mainboard/intel/adlrvp/bootblock.c new file mode 100644 index 0000000..a8f7e41 --- /dev/null +++ b/src/mainboard/intel/adlrvp/bootblock.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c new file mode 100644 index 0000000..d963c73 --- /dev/null +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd new file mode 100644 index 0000000..183f1c1 --- /dev/null +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -0,0 +1,44 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x1081000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x80000 + SI_ME@0x81000 0x1000000 + } + SI_BIOS@0x1400000 0xc00000 { + RW_SECTION_A@0x0 0x368000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x357fc0 + RW_FWID_A@0x367fc0 0x40 + } + RW_SECTION_B@0x368000 0x368000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x357fc0 + RW_FWID_B@0x367fc0 0x40 + } + RW_MISC@0x6D0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS)@0x700000 0x100000 + WP_RO@0x800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl new file mode 100644 index 0000000..b758973 --- /dev/null +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <baseboard/ec.h> +#include <baseboard/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + +} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc new file mode 100644 index 0000000..756de4d --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + + diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb new file mode 100644 index 0000000..16f97bf --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -0,0 +1,111 @@ +chip soc/intel/alderlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + register "gen4_dec" = "0x000c0081" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF + device pci 05.0 on end # IPU + device pci 06.0 on end # PEG60 + device pci 07.0 off end # TBT_PCIe0 + device pci 07.1 off end # TBT_PCIe1 + device pci 07.2 off end # TBT_PCIe2 + device pci 07.3 off end # TBT_PCIe3 + device pci 08.0 off end # GNA + device pci 09.0 off end # NPK + device pci 0a.0 off end # Crash-log SRAM + device pci 0d.0 on end # USB xHCI + device pci 0d.1 off end # USB xDCI (OTG) + device pci 0d.2 off end # TBT DMA0 + device pci 0d.3 off end # TBT DMA1 + device pci 0e.0 off end # VMD + device pci 10.0 off end + device pci 10.1 off end + device pci 10.2 on end # CNVi: BT + device pci 10.6 off end # THC0 + device pci 10.7 off end # THC1 + device pci 11.0 off end + device pci 11.1 off end + device pci 11.2 off end + device pci 11.3 off end + device pci 11.4 off end + device pci 11.5 off end + device pci 12.0 off end # SensorHUB + device pci 12.5 off end + device pci 12.6 off end # GSPI2 + device pci 13.0 off end # GSPI3 + device pci 13.1 off end + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + end + end + end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI + device pci 14.2 off end # Shared RAM + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi + end + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + device pci 16.0 on end # HECI1 + device pci 16.1 off end # HECI2 + device pci 16.2 off end # CSME + device pci 16.3 off end # CSME + device pci 16.4 off end # HECI3 + device pci 16.5 off end # HECI4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 on end # UART2 + device pci 1c.0 on end # RP1 + device pci 1c.1 on end # RP2 + device pci 1c.2 on end # RP3 + device pci 1c.3 on end # RP4 + device pci 1c.4 on end # RP5 + device pci 1c.5 on end # RP6 + device pci 1c.6 on end # RP7 + device pci 1c.7 on end # RP8 + device pci 1d.0 on end # RP9 + device pci 1d.1 on end # RP10 + device pci 1d.2 on end # RP11 + device pci 1d.3 on end # RP12 + device pci 1e.0 off end # UART0 + device pci 1e.1 off end # UART1 + device pci 1e.2 off end # GSPI0 + device pci 1e.3 off end # GSPI1 + device pci 1f.0 on end # eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # PMC + device pci 1f.3 on + chip drivers/intel/soundwire + device generic 0 on + end + end + end # Intel Audio SNDW + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # TH + end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c new file mode 100644 index 0000000..4e3ff8d --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_E10, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..4303faf --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..b61276c --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_A15_IRQ + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..4e6001d --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ + +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct cros_gpio *variant_cros_gpios(size_t *num); + +#endif /*__BASEBOARD_VARIANTS_H__ */
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46054
to look at the new patch set (#2).
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 14 files changed, 468 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46054/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46054
to look at the new patch set (#3).
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU)
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 14 files changed, 473 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46054/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 3:
(12 comments)
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 54: ADL_EC This choice doesn't need a name, see CB:43836
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/board_info.txt:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 6: y I don't think flashrom supports ADL yet.
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/bootblock.c:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 10: const struct pad_config *pads; : size_t num; : : pads = variant_early_gpio_table(&num); : gpio_configure_pads(pads, num); I would replace this with a single function call: variant_configure_early_gpio_pads();
gpio.c also has comments.
https://review.coreboot.org/c/coreboot/+/46054/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/46054/2/src/mainboard/intel/adlrvp/... PS2, Line 2: SI_ALL@0x0 0x1081000 { Specifying the offset and size of everything isn't necessary. For CBFSes, the size should be unconstrained so that they fill all available space. I think you can use BUILD_TIMELESS=1 to check if the removals change the binary.
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 1: FLASH@0xfe000000 0x2000000 { there's some FLASH_xM aliases that could be used here
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 2: SI_ALL@0x0 0x1081000 { Specifying the offset and size of everything isn't necessary. For CBFSes, the size should be unconstrained so that they fill all available space. I think you can use BUILD_TIMELESS=1 to check if the removals change the binary.
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 16: No ACPI?
https://review.coreboot.org/c/coreboot/+/46054/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46054/2/src/mainboard/intel/adlrvp/... PS2, Line 28: device pci 0d.1 off end # USB xDCI (OTG) nit: please align the `end` keywords
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c:
PS3: nit: rename to early_gpio.c to differentiate from gpio.c in ramstage?
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 15: const struct pad_config *variant_early_gpio_table(size_t *num) : { : *num = ARRAY_SIZE(early_gpio_table); : return early_gpio_table; : } Instead of passing the arrays, I would simply make this a function that programs the table above:
void variant_configure_early_gpio_pads(void) { gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); }
This is much simpler than passing pointers around, isn't it? 😉
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 44: #define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) Is this used?
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 13: const struct pad_config *variant_early_gpio_table(size_t *num); Update the comment and this prototype:
void variant_configure_early_gpio_pads(void);
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46054
to look at the new patch set (#4).
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU)
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 14 files changed, 477 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46054/4
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 4:
(2 comments)
Thanks for starting the review Angel. So quick update for you. rest need code change and will do by tomorrow morning.
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/board_info.txt:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 6: y
I don't think flashrom supports ADL yet.
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+... 😎
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 16:
No ACPI?
will add in incremental patch :) as off now added only till booting romstage early.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/board_info.txt:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 6: y
Nice, but I see that cros-flashrom treats everything starting from Sunrise Point the same. There's differences in descriptor contents starting from Cannon Point (300-series PCH), and upstream flashrom handles these chipsets slightly differently to report the correct information. flashrom can use the descriptor contents as a layout file, but needs to be able to parse it correctly.
Unfortunately I don't have any SPI Programming Guide for ADL. I see that TGL-LP has the FLMAP3 register, which contains the descriptor Major and Minor revision IDs. If TGL-LP and ADL have the same descriptor revision IDs, then I imagine the rest of fields would be the same, which would be good enough to add descriptor support to upstream flashrom.
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 16:
will add in incremental patch :) as off now added only till booting romstage early.
OK, please mention this in the commit message.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 4:
(10 comments)
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 54: ADL_EC
This choice doesn't need a name, see CB:43836
Ack
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/board_info.txt:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 6: y
Nice, but I see that cros-flashrom treats everything starting from Sunrise Point the same.
Ideally flashrom don't expect to see any change as we are in SPI HW-seq mode since SPT PCH where SPI access method for basic operation remain as is.
There's differences in descriptor contents starting from Cannon Point (300-series PCH), and upstream flashrom handles these chipsets slightly differently to report the correct information. flashrom can use the descriptor contents as a layout file, but needs to be able to parse it correctly.
For Descriptor related changes we have IFD and https://review.coreboot.org/q/topic:%22IFDTOOL%22+(status:open%20OR%20status...) lately fixed.
Unfortunately I don't have any SPI Programming Guide for ADL. I see that TGL-LP has the FLMAP3 register, which contains the descriptor Major and Minor revision IDs.
https://review.coreboot.org/c/coreboot/+/44818
If TGL-LP and ADL have the same descriptor revision IDs, then I imagine the rest of fields would be the same, which would be good enough to add descriptor support to upstream flashrom.
I have added those now as part of IFD latest, if you have TGL coreboot or downloaded from CPFE, you could give a try with latest IFD tool
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/bootblock.c:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 10: const struct pad_config *pads; : size_t num; : : pads = variant_early_gpio_table(&num); : gpio_configure_pads(pads, num);
I would replace this with a single function call: variant_configure_early_gpio_pads(); […]
Ack
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 1: FLASH@0xfe000000 0x2000000 {
there's some FLASH_xM aliases that could be used here
Ack
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 2: SI_ALL@0x0 0x1081000 {
Specifying the offset and size of everything isn't necessary. […]
Ack
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 16:
OK, please mention this in the commit message.
Ack
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c:
PS3:
nit: rename to early_gpio.c to differentiate from gpio. […]
Ack
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 15: const struct pad_config *variant_early_gpio_table(size_t *num) : { : *num = ARRAY_SIZE(early_gpio_table); : return early_gpio_table; : }
Instead of passing the arrays, I would simply make this a function that programs the table above:
void variant_configure_early_gpio_pads(void) { gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); }
This is much simpler than passing pointers around, isn't it? 😉
Awesome, this is how it should be. Thanks
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 44: #define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
Is this used?
removed for now, will add with ramstage changes
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 13: const struct pad_config *variant_early_gpio_table(size_t *num);
Update the comment and this prototype: […]
Ack
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46054
to look at the new patch set (#5).
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU) 5. Add empty dsdt.asl to avoid compilation error
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 13 files changed, 397 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46054/5
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46054/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/46054/2/src/mainboard/intel/adlrvp/... PS2, Line 2: SI_ALL@0x0 0x1081000 {
Specifying the offset and size of everything isn't necessary. […]
Ack
https://review.coreboot.org/c/coreboot/+/46054/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46054/2/src/mainboard/intel/adlrvp/... PS2, Line 28: device pci 0d.1 off end # USB xDCI (OTG)
nit: please align the `end` keywords
Ack
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46054
to look at the new patch set (#6).
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU) 5. Add empty dsdt.asl to avoid compilation error
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 13 files changed, 397 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46054/6
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46054
to look at the new patch set (#7).
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU) 5. Add empty dsdt.asl to avoid compilation error
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 13 files changed, 399 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46054/7
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 7: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/46054/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/46054/7/src/mainboard/intel/adlrvp/... PS7, Line 14: GENERATE_SMBIOS_TABLES This should default to yes already, no need to select it
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/board_info.txt:
https://review.coreboot.org/c/coreboot/+/46054/3/src/mainboard/intel/adlrvp/... PS3, Line 6: y
Nice, but I see that cros-flashrom treats everything starting from Sunrise Point the same.
Ideally flashrom don't expect to see any change as we are in SPI HW-seq mode since SPT PCH where SPI access method for basic operation remain as is.
Right, flashrom uses hwseq mode from SPT onwards, but it reads the IFD contents from the flash chip to know which regions it has. This is useful to only reflash the BIOS region, for instance 😊
There's differences in descriptor contents starting from Cannon Point (300-series PCH), and upstream flashrom handles these chipsets slightly differently to report the correct information. flashrom can use the descriptor contents as a layout file, but needs to be able to parse it correctly.
For Descriptor related changes we have IFD and https://review.coreboot.org/q/topic:%22IFDTOOL%22+(status:open%20OR%20status...) lately fixed.
Alright, so 500-series and 600-series PCH IFD layout should be pretty much the same. Thanks for confirming.
Unfortunately I don't have any SPI Programming Guide for ADL. I see that TGL-LP has the FLMAP3 register, which contains the descriptor Major and Minor revision IDs.
Oh, wonderful! I didn't know about this change. Thanks!
If TGL-LP and ADL have the same descriptor revision IDs, then I imagine the rest of fields would be the same, which would be good enough to add descriptor support to upstream flashrom.
I have added those now as part of IFD latest, if you have TGL coreboot or downloaded from CPFE, you could give a try with latest IFD tool
Alright, will do. Thank you!
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46054
to look at the new patch set (#8).
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU) 5. Add empty dsdt.asl to avoid compilation error
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 13 files changed, 398 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46054/8
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46054/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/46054/7/src/mainboard/intel/adlrvp/... PS7, Line 14: GENERATE_SMBIOS_TABLES
This should default to yes already, no need to select it
Ack
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46054
to look at the new patch set (#9).
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU) 5. Add empty dsdt.asl to avoid compilation error
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 13 files changed, 398 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46054/9
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 9:
Hi Angel,
if you could take a look further if you have some free time.
Thanks, Subrata
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46054/9/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/46054/9/src/mainboard/intel/adlrvp/... PS9, Line 62: nit: extra space
https://review.coreboot.org/c/coreboot/+/46054/9/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/46054/9/src/mainboard/intel/adlrvp/... PS9, Line 12: subdirs-y += ../common I don't see a src/mainboard/intel/common
https://review.coreboot.org/c/coreboot/+/46054/9/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/46054/9/src/mainboard/intel/adlrvp/... PS9, Line 34: 0 nit: space afteR )
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46054
to look at the new patch set (#10).
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU) 5. Add empty dsdt.asl to avoid compilation error
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 13 files changed, 397 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46054/10
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46054/9/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/46054/9/src/mainboard/intel/adlrvp/... PS9, Line 62:
nit: extra space
Ack
https://review.coreboot.org/c/coreboot/+/46054/9/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/46054/9/src/mainboard/intel/adlrvp/... PS9, Line 12: subdirs-y += ../common
I don't see a src/mainboard/intel/common
correct, should get cleaned in TGL mainboard too
https://review.coreboot.org/c/coreboot/+/46054/9/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/46054/9/src/mainboard/intel/adlrvp/... PS9, Line 34: 0
nit: space afteR )
Ack
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 10:
HI Angel, Tim, if you could take a look further if you have some free time.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 10: Code-Review+2
LGTM, it's a good starting point to get ADL build-tested. Thank you!
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
Patch Set 10:
Patch Set 10: Code-Review+2
LGTM, it's a good starting point to get ADL build-tested. Thank you!
Yup Angel and honestly thank you for taking time for review, i have learn something really new in this course from .fmd side. thanks for that review comment =.
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46054 )
Change subject: mb/intel/adlrvp: Add initial ADL-P mainboard code ......................................................................
mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU) 5. Add empty dsdt.asl to avoid compilation error
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46054 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_info.txt A src/mainboard/intel/adlrvp/bootblock.c A src/mainboard/intel/adlrvp/chromeos.c A src/mainboard/intel/adlrvp/chromeos.fmd A src/mainboard/intel/adlrvp/dsdt.asl A src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc A src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 13 files changed, 397 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig new file mode 100644 index 0000000..27c3957 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -0,0 +1,86 @@ +if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select DRIVERS_I2C_HID + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_USB_ACPI + select DRIVERS_SPI_ACPI + select SOC_INTEL_ALDERLAKE + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + +config MAINBOARD_DIR + string + default "intel/adlrvp" + +config VARIANT_DIR + string + default "adlrvp_p" + +config GBB_HWID + string + depends on CHROMEOS + default "ADLRVPP" + +config MAINBOARD_PART_NUMBER + string + default "adlrvp" + +config MAINBOARD_FAMILY + string + default "Intel_adlrvp" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +choice + prompt "ON BOARD EC" + default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P + default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC + help + This option allows you to select the on board EC to use. + Select whether the board has Intel EC or Chrome EC + +config ADL_CHROME_EC + bool "Chrome EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_ACPI + +config ADL_INTEL_EC + bool "Intel EC" + select EC_ACPI + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC +endchoice + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + +config UART_FOR_CONSOLE + int + default 0 +endif diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name new file mode 100644 index 0000000..0d54bb9 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -0,0 +1,8 @@ +config BOARD_INTEL_ADLRVP_P + bool "Alderlake-P RVP" + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + +config BOARD_INTEL_ADLRVP_P_EXT_EC + bool "Alderlake-P RVP with Chrome EC" + select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc new file mode 100644 index 0000000..eb4a981 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/adlrvp/board_info.txt b/src/mainboard/intel/adlrvp/board_info.txt new file mode 100644 index 0000000..be99df8 --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Alderlake rvp +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/adlrvp/bootblock.c b/src/mainboard/intel/adlrvp/bootblock.c new file mode 100644 index 0000000..95f7497 --- /dev/null +++ b/src/mainboard/intel/adlrvp/bootblock.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <bootblock_common.h> + +void bootblock_mainboard_init(void) +{ + variant_configure_early_gpio_pads(); +} diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c new file mode 100644 index 0000000..d963c73 --- /dev/null +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd new file mode 100644 index 0000000..4866662 --- /dev/null +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -0,0 +1,44 @@ +FLASH@0xfe000000 32M { + SI_ALL 0x1081000 { + SI_DESC 0x1000 + SI_EC 0x80000 + SI_ME + } + SI_BIOS@0x1400000 0xc00000 { + RW_SECTION_A 0x368000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x357fc0 + RW_FWID_A 0x40 + } + RW_SECTION_B 0x368000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) 0x357fc0 + RW_FWID_B 0x40 + } + RW_MISC 0x30000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + RW_ELOG(PRESERVE) 0x4000 + RW_SHARED 0x4000 { + SHARED_DATA 0x2000 + VBLOCK_DEV 0x2000 + } + RW_VPD(PRESERVE) 0x2000 + RW_NVRAM(PRESERVE) 0x6000 + } + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS) 0x100000 + WP_RO { + RO_VPD(PRESERVE) 0x4000 + RO_SECTION { + FMAP 0x800 + RO_FRID 0x40 + RO_FRID_PAD 0x7c0 + GBB 0x3000 + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl new file mode 100644 index 0000000..fca3242 --- /dev/null +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + +} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc new file mode 100644 index 0000000..9b21a1b --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_gpio.c diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb new file mode 100644 index 0000000..e16de65 --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -0,0 +1,111 @@ +chip soc/intel/alderlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + register "gen4_dec" = "0x000c0081" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF + device pci 05.0 on end # IPU + device pci 06.0 on end # PEG60 + device pci 07.0 off end # TBT_PCIe0 + device pci 07.1 off end # TBT_PCIe1 + device pci 07.2 off end # TBT_PCIe2 + device pci 07.3 off end # TBT_PCIe3 + device pci 08.0 off end # GNA + device pci 09.0 off end # NPK + device pci 0a.0 off end # Crash-log SRAM + device pci 0d.0 on end # USB xHCI + device pci 0d.1 off end # USB xDCI (OTG) + device pci 0d.2 off end # TBT DMA0 + device pci 0d.3 off end # TBT DMA1 + device pci 0e.0 off end # VMD + device pci 10.0 off end + device pci 10.1 off end + device pci 10.2 on end # CNVi: BT + device pci 10.6 off end # THC0 + device pci 10.7 off end # THC1 + device pci 11.0 off end + device pci 11.1 off end + device pci 11.2 off end + device pci 11.3 off end + device pci 11.4 off end + device pci 11.5 off end + device pci 12.0 off end # SensorHUB + device pci 12.5 off end + device pci 12.6 off end # GSPI2 + device pci 13.0 off end # GSPI3 + device pci 13.1 off end + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + end + end + end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI + device pci 14.2 off end # Shared RAM + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi + end + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + device pci 16.0 on end # HECI1 + device pci 16.1 off end # HECI2 + device pci 16.2 off end # CSME + device pci 16.3 off end # CSME + device pci 16.4 off end # HECI3 + device pci 16.5 off end # HECI4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 on end # UART2 + device pci 1c.0 on end # RP1 + device pci 1c.1 on end # RP2 + device pci 1c.2 on end # RP3 + device pci 1c.3 on end # RP4 + device pci 1c.4 on end # RP5 + device pci 1c.5 on end # RP6 + device pci 1c.6 on end # RP7 + device pci 1c.7 on end # RP8 + device pci 1d.0 on end # RP9 + device pci 1d.1 on end # RP10 + device pci 1d.2 on end # RP11 + device pci 1d.3 on end # RP12 + device pci 1e.0 off end # UART0 + device pci 1e.1 off end # UART1 + device pci 1e.2 off end # GSPI0 + device pci 1e.3 off end # GSPI1 + device pci 1f.0 on end # eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # PMC + device pci 1f.3 on + chip drivers/intel/soundwire + device generic 0 on + end + end + end # Intel Audio SNDW + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # TH + end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c new file mode 100644 index 0000000..d45bf8e --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_E10, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), +}; + +void variant_configure_early_gpio_pads(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..b61276c --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_A15_IRQ + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..7a8f444 --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); + +void variant_configure_early_gpio_pads(void); + +#endif /*__BASEBOARD_VARIANTS_H__ */
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