Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Eric Peers, Felix Held.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56228 )

Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
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Patch Set 4:

(3 comments)

File src/soc/amd/common/block/include/amdblocks/lpc.h:

https://review.coreboot.org/c/coreboot/+/56228/comment/6f584f00_b5df883f 
PS3, Line 121: LPC_ROM_DMA_EC_HOST_CONTROL		0xb8
PPR 55570 has this register definition. On PPR 56969 it seems the registers are not clearly documented. Hope they are identical?

File src/soc/amd/common/block/lpc/spi_dma.c:

https://review.coreboot.org/c/coreboot/+/56228/comment/52aba012_aef2b8c0 
PS3, Line 103: ctrl |= LPC_ROM_DMA_CTRL_ERROR; /* Clear error */
This is read-only bit as per PPR. Even if it is RW, when this bit is set it indicates an error.

https://review.coreboot.org/c/coreboot/+/56228/comment/074a73b9_90259070 
PS3, Line 209: val |= BIT(6);
Is this the magic bit that needs to be set? A macro for that bit? What does this bit do to make the DMA function properly?