[S] Change in coreboot[main]: Kconfig: Place XIP components and FIT at high flash addresses

[Shuo Liu (Code Review)]

Attention is currently required from: Andrey Petrov, Angel Pons, Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Julius Werner, Patrick Rudolph, Ronak Kanabar, Tim Chu, Yu-Ping Wu.

Hello Andrey Petrov, Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Julius Werner, Patrick Rudolph, Ronak Kanabar, Tim Chu, Yu-Ping Wu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86570?usp=email

to look at the new patch set (#10).

Change subject: Kconfig: Place XIP components and FIT at high flash addresses
......................................................................

Kconfig: Place XIP components and FIT at high flash addresses

By default, CACHE_ROM_SIZE is limited to 16MB, but still covers the
whole CBFS. When CBFS spans larger than 16MB, XIP components and FIT
might be laid outside the cached region.

Add XIP_AT_HIGH_ADDR to place XIP components and FIT as high as
possible so that always to maximize the opportunity for them to being
cached.

Select XIP_AT_HIGH_ADDR for intel Granite Rapids SoC.

Change-Id: I8eb469fdcd18d01652979f28049fe1ea3b59311c
Signed-off-by: Shuo Liu 
Signed-off-by: Gang Chen 
---
M Makefile.mk
M src/Kconfig
M src/cpu/intel/fit/Makefile.mk
M src/drivers/intel/fsp2_0/Makefile.mk
M src/security/vboot/Makefile.mk
M src/soc/intel/xeon_sp/gnr/Kconfig
6 files changed, 23 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/86570/10