Change in coreboot[master]: soc/amd/picasso/Makefile: Verify bootblock size is power of two
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40808 )
Change subject: soc/amd/picasso/Makefile: Verify bootblock size is power of two ......................................................................
soc/amd/picasso/Makefile: Verify bootblock size is power of two
Enabling caching for bootblock requires its size to be a power of two. This is because MTRRs have this requirement.
BUG=b:153675909 TEST=Changed bootblock size and saw a build error
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Idede916cbc75bb0fecd729219b92dc9046c23d78 --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/40808/1
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b04e1e9..d137aba 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -189,6 +189,12 @@ # This address must match the BOOTBLOCK logic in arch/x86/memlayout.ld. PSP_BIOSBIN_DEST=$(shell printf "%x" $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) 0x10) $(PSP_BIOSBIN_SIZE)))
+# MTRRs sizes must be a power of two. Ensure the bootblock has a compatible size +# so we can enable caching. +ifneq ($(call is-power-of-two,$(PSP_BIOSBIN_SIZE)),1) +$(error Bootblock size $(PSP_BIOSBIN_SIZE) is not a power of two.) +endif + # type = 0x63 ifeq ($(CONFIG_HAVE_ACPI_RESUME),y) PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS)
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40808 )
Change subject: soc/amd/picasso/Makefile: Verify bootblock size is power of two ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40808/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40808/3//COMMIT_MSG@10 PS3, Line 10: This is because MTRRs have this requirement. You could have just aligned _bootblock in CB:38691 to meet MTRR requirements? Admittedly, for picasso bootblock is compressed in the flash, but worst-case you are almost doubling the DRAM reserve.
Related bug, fixing of which might remove bootblock size reference from the Makefile: https://review.coreboot.org/c/coreboot/+/37490/12/src/soc/amd/picasso/Makefi...
Raul Rangel has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40808 )
Change subject: soc/amd/picasso/Makefile: Verify bootblock size is power of two ......................................................................
Abandoned
Not working on this
-
Kyösti Mälkki (Code Review) -
Raul Rangel (Code Review)