Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27405
Change subject: src/{ec,include,lib}: Use "foo *bar" instead of "foo* bar" ......................................................................
src/{ec,include,lib}: Use "foo *bar" instead of "foo* bar"
Change-Id: I447aaa1850b7e8b514a8c4c04bf5b426d3d1cd0a Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/ec/google/chromeec/crosec_proto.c M src/include/cpu/amd/car.h M src/lib/rtc.c 3 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/27405/1
diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c index 1a8ffb9..2529854 100644 --- a/src/ec/google/chromeec/crosec_proto.c +++ b/src/ec/google/chromeec/crosec_proto.c @@ -24,7 +24,7 @@ #include "ec_message.h"
/* Common utilities */ -void * __weak crosec_get_buffer(size_t size, int req) +void *__weak crosec_get_buffer(size_t size, int req) { printk(BIOS_DEBUG, "crosec_get_buffer() implementation required.\n"); return NULL; diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 288edb2..359fa6b 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -4,14 +4,14 @@ #include <arch/cpu.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -asmlinkage void * post_cache_as_ram(void); +asmlinkage void *post_cache_as_ram(void); asmlinkage void cache_as_ram_new_stack(void);
void disable_cache_as_ram(void);
void asmlinkage early_all_cores(void);
-void * asmlinkage romstage_main(unsigned long bist); +void *asmlinkage romstage_main(unsigned long bist); void asmlinkage romstage_after_car(void);
#endif diff --git a/src/lib/rtc.c b/src/lib/rtc.c index bd98590..c5c157f 100644 --- a/src/lib/rtc.c +++ b/src/lib/rtc.c @@ -31,7 +31,7 @@ 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 };
-static const char * const weekdays[] = { +static const char *const weekdays[] = { "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", };